• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.210-216
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• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2010.11a
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• pp.167-169
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• 2010

Electronic control units for propulsion systems are devices which compute control algorithm by processing the systems' internal sensor signals. Due to the effect of transmission between sensors and a control unit, previous analog systems have drawbacks of signal attenuation and susceptibility to noises. However, a digital sensor can be less influenced by the electrical cable line as it includes sensor, AMP, and AD converter in one module. In addition, it can reduce the process time for control algorithm because extra S/W filtering process is not needed. The current study shows how to process signals for an electronic control unit using digital sensors.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.460-465
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• 2007

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB{\sim}-0.63LSB$ and $0.53LSB{\sim}-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.3
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• pp.32-39
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• 2003

The output voltage of synchronous generator is regulated constantly by field current control in excitation system High frequency PWM converter (current control mode buck converter) type excitation systam fer synchronous generator is able to control exciter current when the load change happened. This paper deals with the design and evaluation of the excitation system for a synchronous generator to improve the steady state and transient stability. The simulation and experimental results show that the proposed excitation system is able to improve the response time by the DVR(digital voltage regulator) of 50[kW] synchronous generator.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.3
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• pp.332-340
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• 2019

Electronic warfare systems are needed to be advantageous in the modern war. Many radar threat signals with various frequency spectrums and complicated techniques exist. For detecting the threats, a receiver with wide and narrow-band digital processing is needed. To process a wide-band searching mode, a polyphase filter bank has become the architecture of choice to efficiently detect threats. A polyphase N-path filter aligns the re-sampled time series in each path, and a discrete Fourier transform aligns phase and separates the sub-channel baseband aliases. Multiple threats and CW are detected or rejected when the signals are received in different sub-channels. And also, to process a narrow-band precision mode, a direct down converter is needed to reduce aliasing by using a decimation filter. These digital logics are designed in a FPGA. This paper shows how to design and develop a wide and narrow-band digital receiver that is capable to detect the threats.

• Journal of Power Electronics
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• v.6 no.2
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• pp.178-185
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• 2006

Recently, the demand for the development of high quality and high-speed laser printers and efficient power utilization has required. Among complicated electro-mechanic devices in laser printers, the toner-fusing unit consumes above 90[%] of all electrical energy needed for printing devices. Therefore, the development of a more effective energy-saving toner fusing process becomes a significant task in great demand. Generally, there are several ways to implement a fusing unit. Among them this paper presents a new induction heating method. The proposed induction heating method enables the increase of coupling coefficient between heating coil and heat roller which also increases total energy transfer efficiency. Therefore, the proposed IH (Induction Heating) inverter system provides very fast W.U.T. (Warm UP Time) as well as higher efficiency. Through experimental results, the proposed control system is verified.

• Progress in Medical Physics
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• v.3 no.1
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• pp.71-78
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• 1992

This study describes the design of the biophysiological signal processing analyzer which can collect and analyze the biosignal raw data. System hardware is consisted of the IBM PC AT. pre-amplifier. AID converter, Counter/Timer. and RS-232C processor. Biophysiological signal data were processed by the software digital filter. FFT and graphic processing routine. The tachogram and FFT of the the peak to peak interval time was accomplished by the Graphic user interface software using the biophysiological signal processed data. Using this system. the powerspectrum of the heart rate variability during the long term could be observed. Experimental results of this system approach our purpose. which is improved the cost performance. easy to use. reducing raw-data noise and optimizing model for digital filter.

• Journal of Electrical Engineering and Technology
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• v.5 no.1
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• pp.61-69
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• 2010

This paper presents a study of a DFIG wind power generation system for real-time simulations. For real-time simulations, the Real-Time Digital Simulator (RTDS) and its user friendly interface simulation software RSCAD are used. A 2.2MW grid-connected variable speed DFIG wind power generation system is modeled and analyzed in this study. The stator-flux oriented vector control scheme is applied to the stator/rotor side converter control, and the back-to-back PWM converters are implemented for the decoupled control. The real-wind speed signal extracted by an anemometer is used for a realistic, reliable and accurate simulation analysis. Block diagrams, a mathematical presentation of the DFIG and a control scheme of the stator/rotor-side are introduced. Real-time simulation cases are carried out and analyzed for the validity of this work.

• Journal of Power Electronics
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• v.18 no.2
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• pp.432-444
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• 2018

This paper presents a capacitor voltage balancing topology using a three-level boost converter (TLBC) for a neutral point clamped (NPC) three-level inverter fed surface permanent magnet synchronous motor drive (SPMSM). It enhanced the performance of the drive in terms of its voltage THD and torque pulsation. The main attracting feature of the proposed control is the boosting of the input voltage and at the same time the balancing of the capacitor voltages. This control also reduces the computational complexity. For the purpose of close loop vector control, a software based cost effective resolver to digital converter RDC-less estimation is implemented to calculate the speed and position. The proposed drive is simulated in the MATLAB/SIMULINK environment and an experimental investigation using dSPACE DS1104 validates the proposed drive system at different operating condition.