Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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Capacitor Voltage Boosting and Balancing using a TLBC for Three-Level NPC Inverter Fed RDC-less PMSM Drives

  • Received : 2017.04.05
  • Accepted : 2017.10.21
  • Published : 2018.03.20
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Abstract

This paper presents a capacitor voltage balancing topology using a three-level boost converter (TLBC) for a neutral point clamped (NPC) three-level inverter fed surface permanent magnet synchronous motor drive (SPMSM). It enhanced the performance of the drive in terms of its voltage THD and torque pulsation. The main attracting feature of the proposed control is the boosting of the input voltage and at the same time the balancing of the capacitor voltages. This control also reduces the computational complexity. For the purpose of close loop vector control, a software based cost effective resolver to digital converter RDC-less estimation is implemented to calculate the speed and position. The proposed drive is simulated in the MATLAB/SIMULINK environment and an experimental investigation using dSPACE DS1104 validates the proposed drive system at different operating condition.

Keywords

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Fig. 1. Schematic diagram of the proposed PMSM drive system.

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Fig. 2. Firing signals of the two switches and inductor current ofthe TLBC.

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Fig. 3. Capacitor voltage balancing using the TLBC for the entiretime period T.

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Fig. 4. Schematic diagram of the capacitor voltage balancingcircuit of the TLBC circuit.

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Fig. 5. Schematic of the RDC-less position estimation.

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Fig. 6. Simulation results of capacitor voltages at the loadingcondition without the TLBC circuit.

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Fig. 7. Simulation results of capacitor voltages at the loadingcondition with the TLBC circuit.

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Fig. 8. Simulation result of the starting response of a PMSMdrive.

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Fig. 9. Simulation result of a PMSM drive at load changing.

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Fig. 10. Simulation result of a PMSM drive at speed changing.

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Fig. 11. Voltage THD of a two-level inverter fed PMSM.

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Fig. 12. Voltage THD of a three-level NPC inverter fed PMSM.

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Fig. 13. Schematic diagram of a hardware implementation of the proposed drive system.

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Fig. 14. Experimental setup.

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Fig. 15. Experimental results of the resolver output signal at: (a) 0o shaft rotation, (b) 90o shaft rotation, (c) 180o shaft rotation, (d) 270oshaft rotation, (e) 360o shaft rotation.

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Fig. 16. Experimental results of a modulated sine and cosineoutput signal.

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Fig. 17. Experimental results of a demodulated sine and cosinesignal.

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Fig. 18. Experimental results of demodulated and modulated sinewaves with the position angle of the rotor shaft.

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Fig. 19. Experimental waveforms of the inductor current andswitching pulses for a three-level boost converter (pulses to S1and S2 5V/div and inductor current 500mA/div).

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Fig. 20. Experimental waveforms of the input voltage, outputcapacitor voltages and inductor current of a three-level boostconverter (capacitor voltage 150V/div, input dc voltage Vdc200V/div, inductor current 250mA/div).

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Fig. 21. Experimental result of the capacitor voltage boostingand balancing (capacitor voltage 150V/div, input dc voltage200V/div, capacitor voltage difference 1V/div).

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Fig. 22. Experimental result of the starting response of a PMSMdrive (speed 450 rpm/div and stator current 5A/div).

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Fig. 23. Experimental result of a PMSM drive at load changing(speed 300rpm/div, stator current 5A/div, capacitor voltagedifference 1V/div).

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Fig. 24. Experimental result of a PMSM drive at speed changing(speed 600rpm/div, stator current 5A/div, capacitor voltagedifference 1V/div).

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Fig. 25. Efficiency of the proposed PMSM drive.

TABLE I PARAMETERS OF THE DRIVE SYSTEM

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