• 한국전기전자재료학회논문지
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• 제22권6호
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• pp.457-461
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• 2009

In this paper, barrier height between Ni-silicide and source/drain is reduced utilizing Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. It is shown that the barrier height is decreased by Pd incorporation and is dependent on the Pd thickness. Therefore, Ni-silicide using the Pd stacked structure is promising for high performance nano-cale PMOSFET.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.10-11
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• 2006

In this study, the Ni/Co/TiN (6/2/25 nm) structure was deposited for thermal stability estimation. Vacuum (30 mTorrs) annealing was carried out to compare with furnace annealing in nitrogen ambient. The proposed Ni/Co/TiN structure exhibited low temperature silicidation and wide range of rapid thermal process (RTP) windows. The sheet resistance was too high to measure after furnace annealing at $600^{\circ}C$ due to the thin thickness (15 nm) of the nickel silicide. However, the sheet resistance maintained stable characteristics up to $600^{\circ}C$ for 30 min after vacuum annealing. Therefore, the low resistance of thin film nickel silicide was obtained by vacuum annealing at $600^{\circ}C$.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
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• pp.66-67
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• 1995

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of Information Display
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• 제1권1호
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• pp.63-69
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• 2000

In order to improve both the level and the stability of electron emission, Mo and Co silicides were formed from Mo mono-layer and Ti/Co bi-layers on single crystal silicon field emitter arrays (FEAs), respectively. Using the slope of Fowler-Nordheim curve and tip radius measured from scanning electron microscopy (SEM), the effective work function of Mo and Co silicide FEAs were calculated to be 3.13 eV and 2.56 eV, respectively. Compared with silicon field emitters, Mo and Co silicide exhibited 10 and 34 times higher maximum emission current, 10 V and 46 V higher device failure voltage, and 6.1 and 4.8 times lower current fluctuation, respectively. Moreover, the emission currents of the silicide FEAs depending on vacuum level were almost the same in the range of $10^{-9}{\sim}10^{-6}$ torr. This result shows that silicide is robust in terms of anode current degradation due to the absorption of air molecules.

• 전자공학회논문지D
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• 제35D권7호
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• pp.72-78
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• 1998

This paper is focused on the fabrication of reliable novel antifuse, which could operate at low voltage along with the improvement in OFF and ON-state properties. The fabricated antifuse consists of Al/BaTi$_{2}$O$_{3}$/SiO$_{2}$/TiW-silicide structure. Through the systematic analyses for bottom metal and the intermetallic insulator, material and electri cproperties were investiaged. TiW-silicide as the bottom electrode had smooth surface with average roughness of 11.angs. at 10X10.mu.m$^{2}$ and was bing kept as-deposited SiO$_{2}$ film stable. Amorphous BaTi$_{2}$O$_{3}$ film as the another insulator was chosen because of its low breakdown strength (2.5MV/cm). breakdown voltage of antifuse is remarkably reduced by using BaTi$_{2}$O$_{3}$ film, and leakage current of that maintained low level due to the SiO$_{2}$ film. Low ON-resistance (46.ohm./.mu.m$^{2}$) and low programming voltage(9.1V) can be obtained in theses antifuses with 220.angs. double insulator layer and 19.6X10$^{-6}$ cm$^{2}$ area, while keeping sufficient OFF-state reliability (less than 1nA).

• 한국재료학회지
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• 제12권11호
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.667-670
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• 2003

Ni-silicide has low thermal stabiliy. This point is obstacle to apply NiSi to devices. So In this paper, we have studied for obtain thermal stability and analysis of dopant dependency of NiSi. And then we applied Ni-silicide to devices. To improvement of thermal stability, we deposit Ni70/Co10/Ni30/TiN100 to sample. Co midlayer is enhanced thermal stability of NiSi. Co/Ni/TiN, this structure show very difference between n-poly and p-poly in sheet resistance. But Ni/Co/Ni/TiN, structure show less difference. Also junction leakage is good.

• 대한전자공학회논문지SD
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• 제38권1호
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• pp.23-29
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• 2001

아날로그용 다결정 실리콘 커패시터를 Ti-실리사이드 공정으로 제조하여 실리사이드에의한 커패시터의 전기적 특성 변화를 조사하였다. 커패시터의 선형 특성을 개선시키기 위해서는 두 전극으로 사용되는 다결정실리콘의 물성이 동일해야한다. 다결정 실리콘들은 높은 불순물 농도를 가져야하고 그 크기가 같아야한다. 정전용량 전압 계수(Voltage Coefficient of Capacitance ；VCC)는 아날로그 커패시터의 선형성을 나타내는 계수이며, 커패시터의 구성 물질과 커패시터의 구조에 의존하게 된다. 본 연구에서는 다결정 실리콘을 Ti-실리사이드 함으로써 낮은 정전용량 전압 계수를 얻을 수 있었다. 이것은 실리사이드와 다결정 실리콘사이의 계면에서 기생 정전용량이 발생하여, 커패시터의 단위 면적 당 정전용량이 낮아졌기 때문이다. 그러나 실리사이드 공정동안 하층 다결정 실리콘 근처의 산화막에서 양전하가 형성됨을 전기적 특성으로부터 유추하였다.