• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.137-137
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• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.869-875
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• 2017

Using TCAD simulation, performances of tunnel field-effect transistors (TFETs) was investigated. Drain current-gate voltage types of TFET structure such as single-gate TFET (SG-TFET), double-gate TFET (DG-TFET), L-shaped TFET (L-TFET), and Pocket-TFET (P-TFET) are simulated, and then as dielectric constant of gate oxide and channel length are varied their subthreshold swing (SS) and on-current ($I_{on}$) are compared. On-currents and subthreshold swings of the L-TFET and P-TFET structures with high electric constant and line tunneling were 10 times and 20 mV/dec more than those of the SG-TFET and DG-TFET using point tunneling, respectively. Especially, it is shown that hump effect which dominant current element changes from point tunneling to line tunneling, is disappeared in P-TFET with high-k gate oxide such as $HfO_2$. The analysis of 4 types of TFET structure provides guidelines for the design of new types of TFET structure which concentrate on line tunneling by minimizing point tunneling.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• Korean Journal of Materials Research
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• v.11 no.6
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• pp.448-452
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• 2001

The ZnS:Cu,Cl thick film electroluminescent devices with the stacking type(separated with phosphors and insulator layers) and the composite type (mixed with phosphor and insulator materials) emission layers were fabricated on ITO/glass substrates by the screen printing methods. The opical and electrical properties were investigated as fundations of applied voltages and frequencies. In the stacking type, the luminance was about 58 cd/$\m^2$ at the applied voltage of 400Hz, 200V and increased to 420 cd/$\m^2$ with increasing the frequency to 30Hz. For the composite type devices, the threshold voltage was 45V and the maximum luminance was 670 cd/$\m^2$ at the driving condition of 200V, 30Hz. The value of luminance of the composite type device showed 1.5 times higher than that of stacking type device. The main emission peak was 512 nm of bluish-green color at 1Hz frequency below and shifted to 452 nm in the driving frequency over 5Hz showing the blue omission color. There were no distinct differences of the main emission peaks and color coordinate for both samples.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.413-417
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• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.360-364
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• 2015

Electronic systems based on solid state devices have changed to be more complicated and miniaturized as the electronic systems developed. If the electronic systems are exposed to HPEM (high power electromagnetics), the systems will be destroyed by the coupling effects of electromagnetic waves. Because the HPEM has fast rise time and high voltage of the pulse, the semiconductors are vulnerable to external stress factor such as the coupled electromagnetic pulse. Therefore, we will discuss about malfunction behavior and DFR (destruction failure rate) of the semiconductor caused by amplitude and repetition rate of the pulse. For this experiment, the pulses were injected into the pins of general purpose IC due to the fact that pulse injection test enables the phenomenon after the HPEM is coupled to power cables. These pulses were produced by pulse generator and their characteristics are 2.1 [ns] of pulse width, 1.1 [ns] of pulse rise time and 30, 60, 120 [Hz] of pulse repetition rate. The injected pulses have changed frequency, period and duty ratio of output generated by Timer IC. Also, as the pulse repetition rate increases the breakdown threshold point of the timer IC was reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.716-718
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• 2012

This paper have presented the change for subthreshold characteristics for double gate(DG) MOSFET based on scaling theory and the shape of Gaussian function. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution and consequently potential distributions have been analyzed closely for experimental results, and the subthreshold characteristics have been analyzed for the shape parameters of Gaussian function such as projected range and standard projected deviation. Since this potential model has been verified in the previous papers, we have used this model to analyze the subthreshold chatacteristics. The scaling theory is to sustain constant outputs for the change of device parameters. As a result to apply the scaling theory for DGMOSFET, we know the subthreshold characteristics have been greatly changed, and the change of threshold voltage is bigger relatively.

• Bulletin of the Korean Chemical Society
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• v.32 no.spc8
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• pp.2899-2905
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• 2011

We have demonstrated that TPyPA can be used as an efficient multi-functional material for OLEDs; hole transporting material (HTL), blue and white-light emitter. The device based on TPyPA as the HTL exhibited an external quantum efficiency of 1.7% and a luminance efficiency of 4.2 cd/A; these values are 40% higher than the external quantum efficiency and luminance efficiency of the NPD-based reference device. The device based on TPyPA as a blue-light emitter exhibited an external quantum efficiency of 4.2% and a luminance efficiency of 5.3 $cdA^{-1}$ with CIE coordinates at (0.16, 0.14), the device based on TPyPA as a white-light emitter exhibited an external quantum efficiency of 3.2% and a luminance efficiency of 7.7 $cdA^{-1}$ with CIE coordinates at (0.33, 0.39). Also, TPyPA-based organic solar cell (OSC) exhibited a maximum power conversion efficiency of 0.35%. TPyPA-based organic thin-film transistors (OTFTs) exhibited highly efficient field-effect mobility (${\mu}_{FET}$) of $1.7{\times}10^{-4}cm^2V^{-1}s^{-1}$, a threshold voltage ($V_{th}$) of -15.9 V, and an on/off current ratio of $8.6{\times}10^3$.