• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.2
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• pp.93-97
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• 2003

The crystallization behavior of amorphous silicon is affected by direction and intensity of electric field in FALC（Field-Aided Lateral Crystallization). Electric field was calculated in a simplified model using conductivity data of Mo, a-Si, $SiO_2$and boundary conditions for electric potential at the electrodes. The magnitude of electric field intensity in each corner of cathode was much larger than that in the center of patterns, and the electric field direction was 50~60 degree outside to cathode. And electric field intensity at a relatively small pattern was larger than that of a large pattern.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1999.06a
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• pp.285-303
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• 1999

Thin films of hydrogenated amorphous silicon carbide compounds (a-SixC1x:H) of different compositions were deposited on Si substrate by RF plasma-enhanced chemical vapor deposition (PECVD). Experiments were carried out using silane(SiH4) and methane(CH4) as the gas precursors at 1 Torr and at low substrate temperature (25$0^{\circ}C$). The gas flow rate was changed with every other parameters (pressure, temperature, RF power) fixed. The substrate was Si(100) wafer and all of the films obtained were amorphous. The bonding structure of a-SixC1x:H films deposited was investigated by X-ray photoelectron spectroscopy (XPS) for the film compositions. In addition, the surface morphology of films was investigated by atomic force microscopy (AFM).

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1649-1652
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• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (${\alpha}$- Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated because the 2.5 um fine pattern formation technique is combined with high thermal photo-resist (PR) development. In addition, a novel concept of unique ${\alpha}$-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um finepatterning is a considerably significant technology to obtain higher aperture ratio for higher resolution ${\alpha}$-Si TFT-LCD panel realization.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.13-13
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• 2010

Piezoelectric sensors are extensively used to measure force because of their high sensitivity and low cost. however, the development of device with reduced size but with improved sensitivity is highly important. Low-temperature co-fired ceramic (LTCC) is one of promising materials for this application than a silicon substrate because it has very good electrical and mechanical properties as well as possibility of making various three dimensional (3D) structures. In this work, piezoelectric pressure sensors based on hybrid LTCC technology were presented. The LTCC diaphragms with thickness of $400\;{\mu}m$ were fabricated by laminating 12 green tapes which consist of alumina and glass particle in an organic binder. The piezoelectric sensing layer consists of PZT thin film deposited by RF magnetron sputtering method on between top and bottom Au electrodes. The PZT films deposited on LTCC diaphragms were successfully grown and were analyzed by using X-ray diffraction method (XRD) and field emission scanning electron microscope (FESEM).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.4
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• pp.285-289
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• 2009

Small RFID tag antenna were fabricated on Si substrate and their physical and electrical properties were evaluated. With decreasing the size of tag antenna on Si substrate, small SMD-type RFID tags could be fabricated, which is very useful for various applications including PCB tracking. Firstly, electromagnetic properties on tag antenna pattern were simulated with HFSS. The setup frequency was 13.56 MHz of HF-band RFID. The line-width and line-gap were modeled in the range of $50{\sim}200{\mu}m$. S parameters, SRF, and Q value were calculated from the model. When the line-width and line-gap were 100 urn and the loop-turn was 10, the SRF was 80 MHz and the Q value was ca. 9. When the microstrip antenna pattern of aluminum was fabricated by using DC sputtering, Vpp of ca. 1.6 V was obtained when the reader-tag distance was 40 mm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.395-401
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• 2013

In-situ optical emission spectroscopy (OES) is employed for leak detection in plasma etching system. A misprocessing is reported for significantly reduced silicon etch rate with chlorine gas, and OES is used as a supplementary sensor to analyze the gas phase species that reside in the process chamber. Potential cause of misprocessing reaches to chamber O-ring wear out, MFC leaks, and/or leak at gas delivery line, and experiments are performed to funnel down the potential of the cause. While monitoring the plasma chemistry of the process chamber using OES, the emission trace for nitrogen species is observed at the chlorine gas supply. No trace of nitrogen species is found in other than chlorine gas supply, and we found that the amount of chlorine gas is slightly fluctuating. We successfully found the root cause of the reported misprocessing which may jeopardize the quality of thin film processing. Based on a quantitative analysis of the amount of nitrogen observed in the chamber, we conclude that the source of the leak is the fitting of the chlorine mass flow controller with the amount of around 2-5 sccm.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.12-14
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• 2005

Inductively Coupled Plasma Chemical Vapor Deposition(ICP-CVD)를 이용하여 공정온도 $150^{\circ}C$에서 Nanocrystalline silicon (nc-Si) 박막을 증착하였다. 실험에서 헬륨(He)가스, 수소($H_2$)가스 그리고 헬륨(He)과 수소($H_2$)의 혼합가스로 희석한 사일렌($SiH_4$)을 반응가스로 이용하였다. 이 혼합가스는 3sccm의 사일렌($SiH_4$)에 헬륨(He)과 수소($H_2$)의 주입율을 20sccm에서부터 60sccm까지 변화시켜 조건을 달리하여 사용했다. 증착한 Nc-Si 박막을 X-ray diffraction (XRD)으로 분석하여 각각의 조건에 대한 Nc-Si 박막의 속성을 연구하였다. 헬륨(He) 또는 수소($H_2$) 혼합가스의 주입율이 커지면서 <111>과 <222>의 최고점(peak)이 더 높아졌으며 결정화 되지 않고 비결정질로 남아 있는 성장층(incubation layer)이 얇아졌다. 이 결과는 nc-Si를 증착할 때 사용한 수소($H_2$) 플라즈마와 헬륨(He) 플라즈마의 효과로 설명할 수 있다. 실험을 통해 ICP-CVD로 증착한 nc-Si 박막을 박막 전계효과트랜지스터 (TFT)에서 우수한 특성의 전자수송층(active layer)으로 사용할 수 있는 것을 확인하였다.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1443-1445
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• 1996

Hydrogen passivation enhances the electrical characteristics of poly-Si TFT(Thin Film Transistor). However, the weak Si-H bonds, generated during hydrogenation, degrade the stability of the device. So, we carried out the passivation treatment with $NH_3$ or $N_2$. We compared the effect of $NH_3$ or $N_2$ passivation treatments with that of hydrogenation in terms of stability. Through the $NH_3$ passivation treatment, we obtained the most improved subthreshold swing of 1.2V/decade from the initial subthreshold swing of 1.56V/decade. When electrical stress was given, the $NH_3$ passivated devices showed best electrical stability.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.8
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• pp.481-485
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• 2015

We investigated the effects of annealing on the electrical and thermal properties of ZTO/4H-SiC heterojunction diodes. A ZTO thin film layer was grown on p-type 4H-SiC substrate by using solution process. The ZTO/SiC heterojunction structures annealed at $500^{\circ}C$ show that $I_{on}/I_{off}$ increases from ${\sim}5.13{\times}10^7$ to ${\sim}1.11{\times}10^9$ owing to the increased electron concentration of ZTO layer as confirmed by capacitance-voltage characteristics. In addition, the electrical characterization of ZTO/SiC heterojunction has been carried out in the temperature range of 300~500 K. When the measurement temperature increased from 300 K to 500 K, the reverse current variation of annealed device is higher than as-grown device, which is related to barrier height in the ZTO/SiC interface. It is shown that annealing process is possible to control the electrical characteristics of ZTO/SiC heterojunction diode.