• Journal of Sensor Science and Technology
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• v.9 no.1
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• pp.9-14
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• 2000

Dielectric characteristics of P(VDF/TrFE) film manufactured using spin coating technique have been investigated. To improve the crystallinity and quality of film, the film was three step annealed. Simple etching process and conditions for P(VDF/TrFE) film were established using top electrode as a mask. Poling is performed by several steps. $1.87\;{\mu}m$ thick P(VDF/TrFE) films were obtained with conditions such that the solution of 10 wt% concentration was spun at 3000rpm for 30 seconds. Before poling, dielectric constant and dielectric loss of P(VDF/TrFE) film were 13.5 and 0.042, respectively. After poling, dielectric constant and dielectric loss of P(VDF/TrFE) film were 11.5 and 0.037, respectively.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.8 no.1
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• pp.15-22
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• 2002

We received 2 types flexible packaging films from two companies that laminated PET $16{\mu}m/dry$ lamination/aluminium foil $7{\mu}m/dry$ lamination/CPP $80{\mu}m$ films. For the reason of hot sealing's trouble through filling process, We separated each layer and compared thicks, film types and tested IR, DSC and sensory test. At the result, one sample's thick is different but film types is same between samples. Optimum hot-sealing conditions between two samples is $195^{\circ}C\;and\;210^{\circ}C$. The difference is $15^{\circ}C$. According to test of direct filling packaging process by four face fluid filling machine, two sample's sealing strength of hot-sealing is $4.76kg/cm2/15mm$(sample of optimum hot-sealing condition is $195^{\circ}C$) and $3.84kg/cm2/15mm(210^{\circ}C)$.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.444-444
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• 2011

Recently, patterned magnetic films and elements attract a wide interest due to their technological potentials in ultrahigh-density magnetic recording and spintronic devices. Among those patterned magnetic structures, magnetic anti-dot patterning induces a strong shape anisotropy in the film, which can control the magnetic properties such as coercivity, permeability, magnetization reversal process, and magneto-resistance. While majority of the previous works have been concentrated on anti-dot arrays with a single magnetic layer, there has been little work on multilayered anti-dot arrays. In this work, we report on study of the magnetic properties of bilayered anti-dot system consisting of upper perforated Co layer of 40 nm and lower continuous Ni layer of 5 nm thick, fabricated by photolithography and wet-etching processes. The magnetic hysteresis (M-H) loops were measured with a superconducting-quantum-interference-device (SQUID) magnetometer (Quantum Design: MPMS). For comparison, investigations on continuous Co thin film and single-layer Co anti-dot arrays were also performed. The magnetic-domain configuration has been measured by using a magnetic force microscope (PSIA: XE-100) equipped with magnetic tips (Nanosensors). An external electromagnet was employed while obtaining the MFM images. The MFM images revealed well-defined periodic domain networks which arise owing to the anisotropies such as magnetic uniaxial anisotropy, configurational anisotropy, etc. The inclusion of holes in a uniform magnetic film and the insertion of a uniform thin Ni layer, drastically affected the coercivity as compared with single Co anti-dot array, without severely affecting the saturation magnetization ($M_s$). The observed changes in the magnetic properties are closely related to the patterning that hinders the domain-wall motion as well as to the magneto-anisotropic bilayer structure.

• Journal of the Korean Magnetics Society
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• v.16 no.1
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• pp.75-78
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• 2006

In case of contacts between semiconductor and metal in semiconductor circuits, they become unstable because of thermal budget. To prevent these problems, we use diffusion barrier that has a good thermal stability between metal and semiconductor. So we consider the diffusion barrier to prevent the increase of contact resistance between the interfaces of metals and semiconductors, and the increase of resistance and the reaction between the interfaces. In this paper we deposited tungsten boron carbon nitride (W-B-C-N) thin film on silicon substrate. The impurities of the $1000\;{\AA}-thick$ W-B-C-N thin films provide stuffing effect for preventing the inter-diffusion between metal thin films $(Cu-2000\;{\AA})$ and silicon during the high temperature $(700\~1000^{\circ}C)$ annealing process.

• Journal of Electrochemical Science and Technology
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• v.8 no.1
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• pp.15-24
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• 2017

A comparative study was performed on the passivating abilities of surface films generated on lithium titanate (LTO; $Li_4Ti_5O_{12}$) electrodes during pre-cycling at two different rates. The surface film deposited at a faster pre-cycling rate (i.e., 0.5 C) is irregularly shaped and unevenly covers the LTO electrode. Owing to the incomplete coverage of the protective film, this LTO electrode exhibits poor passivating ability. Additional electrolyte decomposition and concomitant film deposition occur during subsequent charge/discharge cycles. As a result of the thick surface film, severe cell polarization occurs and eventually causes cell failure. However, pre-cycling the Li/LTO cell at a slower rate (0.1 C) improves cell polarization and capacity retention; this occurs because the surface film uniformly covers the LTO electrode and provides strong passivation. Accordingly, there is no significant film deposition during subsequent charge/discharge cycling. Additionally, self-discharge is reduced during high-temperature storage.

• Journal of the Korean Magnetics Society
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• v.9 no.2
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• pp.104-110
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• 1999

The effect of the composition and the heat treatment on the magnetic and magnetoresistance properties in AgCo alloy films and Fe/AgCo/Fe trilayers prepared by the co-evaporation method were studied. As the alloy film thickness decreases, especially below 50 nm thick, the magnetoresistance decreases and the saturation field increases significantly. The change of the Co content, heat treatment, and deposition of the Fe under/over-layer were effective to prevent the reduction of the and the increasing of the saturation field. For 40 at.%Co sandwiches, the minimum saturation field was obtained in the 20 nm alloy film with 30nm Fe under-over layer annealed at 300 $^{\circ}C$ for 10 min. Its saturation field and the MR ratio were 1.01 kOe 5.16% respectively.

• Journal of the Korean Ceramic Society
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• v.39 no.4
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• pp.377-385
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• 2002

The possibility of $ZrO_2$ thin film as insulator for Metal-Ferroelectric-Insulator-Semiconductor(MFIS) structure was investgated. $SrBi_2Ta_2O_9$ and $SrBi_2Ta_2O_9$(SBT) thin films were deposited on P-type Si(111) wafer by R. F. magnetron sputtering method. The electrical properties of MFIS gate were relatively improved by inserting the $ZrO_2$ buffer layer. The window memory increased from 0.5 to 2.2V in the applied gate voltage range of 3-9V when the thickness of SBT film increased from 160 to 220nm with 20nm thick $ZrO_2$. The maximum value of window memory is 2.2V in Pt/SBT(160nm)/$ZrO_2$(20nm)/Si structure with the optimum thickness of $ZrO_2$. These memory windows are sufficient for practical application of NDRO-FRAM operating at low voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.469-473
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• 2017

We investigated the effect of different thin-film thicknesses (25, 30, and 40 nm) on the electrical performance of solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs). The structural properties of the IZO thin films were investigated by atomic force microscopy (AFM). AFM images revealed that the IZO thin films with thicknesses of 25 and 40 nm exhibit an uneven distribution of grains, which deforms the thin film and degrades the performance of the IZO TFT. Further, the IZO thin film with a thickness of 30 nm exhibits a homogeneous and smooth surface with a low RMS roughness of 1.88 nm. The IZO TFTs with the 30-nm-thick IZO film exhibit excellent results, with a field-effect mobility of $3.0({\pm}0.2)cm^2/Vs$, high Ion/Ioff ratio of $1.1{\times}10^7$, threshold voltage of $0.4({\pm}0.1)V$, and subthreshold swing of $0.7({\pm}0.01)V/dec$. The optimization of oxide semiconductor thickness through analysis of the surface morphologies can thus contribute to the development of oxide TFT manufacturing technology.

• Journal of Surface Science and Engineering
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• v.50 no.5
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• pp.352-359
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• 2017

The growth of nanocrystalline diamond films on a p-type poly silicon substrate was studied using microwave plasma chemical vapor deposition method. A 6 mm thick poly silicon plate was mirror polished and scratched in an ultrasonic bath containing slurries made of 30 cc ethanol and 1 gram of diamond powders having different sizes between 5 and 200 nm. Upon diamond deposition, the specimen scratched in a slurry with the smallest size of diamond powder exhibited the highest diamond particle density and, in turn, fastest diamond film growth rate. Diamond deposition was carried out applying different DC bias voltages (0, -50, -100, -150, -200 V) to the substrate. In the early stage of diamond deposition up to 2 h, the effect of voltage bias was not prominent probably because the diamond nucleation was retarded by ion bombardment onto the substrate. After 4 h of deposition, the film growth rate increased with the modest bias of -100 V and -150 V. With a bigger bias condition(-200 V), the growth rate decreased possibly due to the excessive ion bombardment on the substrate. The film grown under -150V bias exhibited the lowest contact angle and the highest surface roughness, which implied the most hydrophilic surface among the prepared samples. The film growth rate increased with the apparent activation energy of 21.04 kJ/mol as the deposition temperature increased in the range of $300{\sim}600^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.