• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.5
• /
• pp.285-289
• /
• 2003

This paper proposes a 10 ${\mu}{\textrm}{m}$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and rnicrornachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation (50$0^{\circ}C$, 1 hr at $H_2O$/O$_2$) and rapid thermal oxidation (RTO) process (105$0^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to 10 ${\mu}{\textrm}{m}$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 1 dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about - 20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.

• Journal of the Korean Ceramic Society
• /
• v.38 no.12
• /
• pp.1150-1154
• /
• 2001

Silicon oxynitride (SiON) thick films using the core layer of silica optical waveguide have been deposited on Si wafer by PECVD at low temperature (32$0^{\circ}C$) were obtained by decomposition of appropriate mixture of (SiH$_4$+$N_2$O+$N_2$) gaseous mixtures under RF power and SiH$_4$/($N_2$O+$N_2$) ratio deposition condition. Prism coupler measurements show that the refractive indices of SiON layers range from 1.4663 to 1.5496. A high SiH$_4$/($N_2$O+$N_2$) of 0.33 and deposition power of 150 W leads to deposition rates of up to 8.67 ${\mu}{\textrm}{m}$/h. With decreasing SiH$_4$/($N_2$O+$N_2$) ratio, the SiON layer become smooth from 41$\AA$ to 6$\AA$.

• Proceedings of the KIEE Conference
• /
• 1998.07g
• /
• pp.2536-2538
• /
• 1998

This paper investigates the residual stress of tetraethoxysilane (TEOS) and 7wt% phosphosilicate glass (PSG), which are commonly used as a sacrificial layer or etch mask in the fabrication of microelectromechanical systems (MEMS). In order to measure residual stress, $2{\mu}m$ thick TEOS and PSG stress measurement structures are fabricated. Polysilicon is used as the sacrificial layer. First the residual stress of an as-deposited 7wt% PSG flim and TEOS film are measured to be-0.3115% and -0.435%, respectively, which are quite large. These films are annealed from $500^{\circ}C$ to $800^{\circ}C$. Annealing has the effects of reducing residual stress. In the case of the 7wt% PSG film, the residual stress becomes +0.00715% after annealing at $625^{\circ}C$ for 150 minutes. In the case of TEOS film, the residual stress reduces to -0.2134% after same condition. Incidentally, this condition is the same condition for depositing a $2{\mu}m$ thick polysilicon at $625^{\circ}C$ at our low pressure chemical vapor deposition (LPCVD) furnace.

• Korean Journal of Materials Research
• /
• v.19 no.4
• /
• pp.179-185
• /
• 2009

We fabricated thermally evaporated 30 nm-Ni/(20 nm or 60 nm)a-Si:H/Si films to investigate the energy-saving property of silicides formed by rapid thermal annealing (RTA) at temperatures of $350^{\circ}C$, $450^{\circ}C$, $550^{\circ}C$, and $600^{\circ}C$ for 40 seconds. A transmission electron microscope (TEM) and a high resolution X-ray diffractometer (HRXRD) were used to determine the cross-sectional microstructure and phase changes. A UVVIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were employed for near-IR and middle-IR absorbance. Through TEM and HRXRD analysis, for the nickel silicide formed at low temperatures below $450^{\circ}C$, we confirmed columnar-shaped structures with thicknesses of $20{\sim}30\;nm$ that had ${\delta}-Ni^2Si$ phases. Regarding the nickel silicide formed at high temperatures above $550^{\circ}C$, we confirmed that the nickel silicide had more than 50 nm-thick columnar-shaped structures with a $Ni_{31}Si_{12}$ phase. Through UV-VIS-NIR analysis, nickel silicide showed almost the same absorbance in the near IR region as well as ITO. However, in the middle IR region, the nickel silicides with low temperature showed similar absorbance to those from high temperature silicidation.

• Journal of Information Display
• /
• v.4 no.2
• /
• pp.1-6
• /
• 2003

In this paper, we demonstrate that the organic electrophosphorescent device is driven by the organic thin film transistor with spin-coated photoacryl gate insulator. It was found that electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure showed the non-saturated slope in the saturation region and the sub-threshold nonlinearity in the triode region, where we obtained the maximum power luminance that was about 90 $cd/m^2$. Field effect mobility, threshold voltage, and on-off current ratio in 0.45 ${\mu}m$ thick gate dielectric layer were 0.17 $cm^2/Vs$, -7 V, and $10^6$ , respectively. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and cured at 150${\sqsubset}$for 1hr. It was also found that field effect mobility, threshold voltage, on-off current ratio, and sub-threshold slope with 0.45 ${\mu}m$ thick gate dielectric films were 0.134 $cm^2/Vs$, -7 V, and $10^6$ A/A, and 1 V/decade, respectively.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.08a
• /
• pp.240.2-240.2
• /
• 2013

The device scale of flash memory was confronted with quantum mechanical limitation. The next generation memory device will be required a break-through for the device scaling problem. Especially, graphene is one of important materials to overcome scaling and operation problem for the memory device, because ofthe high carrier mobility, the mechanicalflexibility, the one atomic layer thick and versatile chemistry. We demonstrate the hybrid memory consisted with the metal-oxide quantum dots and the mono-layered graphene which was transferred to $SiO_2$ (5 nm)/Si substrate. The 5-nm thick secondary $SiO_2$ layer was deposited on the mono-layered graphene by using ultra-high vacuum sputtering system which base pressure is about $1{\times}10^{-10}$ Torr. The $In_2O_3$ quantum dots were distributed on the secondary $SiO_2$2 layer after chemical reaction between deposited In layer and polyamic acid layer through soft baking at $125^{\circ}C$ for 30 min and curing process at $400^{\circ}C$ for 1 hr by using the furnace in $N_2$ ambient. The memory devices with the $In_2O_3$ quantum dots on graphene monolayer between $SiO_2$ thin films have demonstrated and evaluated for the application of next generation nonvolatile memory device. We will discuss the electrical properties to understating memory effect related with quantum mechanical transport between the $In_2O_3$ quantum dots and the Fermi level of graphene layer.

• ETRI Journal
• /
• v.43 no.5
• /
• pp.909-915
• /
• 2021

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer-scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3-㎛ bowing was observed using the 725-㎛-thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4×10⁷ cm^-2. For lattice-matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725-㎛-thick Si substrate can be used for the large-scale integration of GaAs on Si with less bowing and low TDD.

• Korean Journal of Metals and Materials
• /
• v.48 no.2
• /
• pp.133-140
• /
• 2010

10 nm thick Ni layers were deposited on 200 nm $SiO_2/Si$ substrates using an e-beam evaporator. Then, 60 nm or 20 nm thick ${\alpha}$-Si:H layers were grown at low temperature (<$200^{\circ}C$) by a Catalytic-CVD. NiSi layers were already formed instantaneously during Cat-CVD process regardless of the thickness of the $\alpha$-Si. The resulting changes in sheet resistance, microstructure, phase, chemical composition, and surface roughness with the additional rapid thermal annealing up to $500^{\circ}C$ were examined using a four point probe, HRXRD, FE-SEM, TEM, AES, and SPM, respectively. The sheet resistance of the NiSi layer was 12${\Omega}$/□ regardless of the thickness of the ${\alpha}$-Si and kept stable even after the additional annealing process. The thickness of the NiSi layer was 30 nm with excellent uniformity and the surface roughness was maintained under 2 nm after the annealing. Accordingly, our result implies that the low temperature Cat-CVD process with proposed films stack sequence may have more advantages than the conventional CVD process for nano scale NiSi applications.

• Korean Journal of Metals and Materials
• /
• v.49 no.4
• /
• pp.321-328
• /
• 2011

The 30 nm-thick Ni layers was deposited on a flexible polyimide substrate with an e-beam evaporation. Subsequently, we deposited a Si layer using a catalytic CVD (Cat-CVD) in a hydride amorphous silicon (${\alpha}$-Si:H) process of $T_{s}=180^{\circ}C$ with varying thicknesses of 55, 75, 145, and 220 nm. The sheet resistance, phase, degree of the crystallization, microstructure, composition, and surface roughness were measured by a four-point probe, HRXRD, micro-Raman spectroscopy, FE-SEM, TEM, AES, and SPM. We confirmed that our newly proposed Cat-CVD process simultaneously formed both NiSi and crystallized Si without additional annealing. The NiSi showed low sheet resistance of < $13{\Omega}$□, while carbon (C) diffused from the substrate led the resistance fluctuation with silicon deposition thickness. HRXRD and micro-Raman analysis also supported the existence of NiSi and crystallized (>66%) Si layers. TEM analysis showed uniform NiSi and silicon layers, and the thickness of the NiSi increased as Si deposition time increased. Based on the AES depth profiling, we confirmed that the carbon from the polyimide substrate diffused into the NiSi and Si layers during the Cat-CVD, which caused a pile-up of C at the interface. This carbon diffusion might lessen NiSi formation and increase the resistance of the NiSi.

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.1
• /
• pp.43-47
• /
• 2022

In this study, we demonstrated an eco-friendly thin-metallic-film-based heater which can be operated in water. Based on the materials stability, Mo was selected as the heating element to secure long-term stability. Using a magnetron sputtering, 40 nm-thick Mo layers were deposited onto a glass substrate, followed by the deposition of 60-nm-thick ZnO layer to prevent oxidation during the heater fabrication process. Then, PVB (Polyvinyl Butyral) was applied on top of ZnO layer and an additional glass substrate was placed, which were heated at 150℃ for 2 hr. The PVB was cured with strong adhesion by the processing condition. We operated the Glass/Mo/ZnO/Glass heater in water, and it was shown that the water temperature reached 50℃ within 2 minutes, with a minimal resistance change of the heater. Finally, the heaters exhibit a semi-transparency, and this aesthetic advantage is expected to contribute to the added value of the heater.