• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.247-251
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• 1998

This work presents the analysis of $1\times2$ polymer waveguide thermo-optic switch using asymmetric Y-splitter at the wavelength of 1300nm. Because of the high thermo-optic coefficient of polymeric materials the design of efficient switches were feasible. For the numerical simulation of these switches the finite difference beam propagation method has been employed. Design rules for a $1\times2$ polymeric switch have been defined by using the numerical techniques.

• 한국전기전자재료학회논문지
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• 제11권8호
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• pp.601-606
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• 1998

ZnO thin film had been deposited on the glass by sputtering method, and the electrical and structural properties were investigated. When the rf power was 180W and sputtering was 10 m Torr at room temperature, Al-doped ZnO thin film had the lowest resistivity(1$\times10^{-4}\Omega\cdot{cm}$) and then carrier concentration and Hall mobility were $6.27\times10^{20} cm^{-3} and 22.04 cm^2/V\cdot$s, respectively. The undoped ZnO thin film had about 10$\times10^{14}\Omega\cdot cm$ resistivity when oxygen content was 10% or more at room temperature. When the oxygen content was 50% and below and sputtering pressure was 1.0$\times$1.0 \ulcorner Torr, the surface morphology of thin film observed by SEM was overall uniform.

• E2M - 전기 전자와 첨단 소재
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• 제19권9호
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• pp.28-32
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• 2006

A 7.0-inch transmissive type plastic TFT-LCD was developed at the resolution of 640 $\times$ 3 $\times$ 480 lines (114ppi). All of the processed of TFT, color filter and LC were carried out below $130^{\circ}C$ on PES plastic films. The process conditions of TFT, color filter and LC were optimized for large area TFT-LCD on plastic substrate. The backplane and the color filter was strongly adhered while the panel was bending by using holding spacers.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.138-138
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• 2009

Al, Ga and In doped ZnO thin film were prepared by faing targets sputtering as a function of oxygen gas contents at R.T. Base pressure was $2{\times}10^{-6}torr$, and working pressure was 1mTorr. The properties of thin films on the electrical and optical properties of the deposited films were investigated by using a four-point probe (Chang-min), a Hall Effect measurement (Ecopia) and an UV/VIS spectrometer (HP). The minimum resistivities of AZO, GZO and IZO thin film were $6.5{times}10^{-4}[{\Omega}-cm],5.5{\times}10^{-4}[{\Omega}-cm]$ and $4.29{\times}10^{-4}[{\Omega}-cm]$. The average transmittance of over 80% was seen in the visible range.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.286-289
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• 1999

In order to detect the partial discharge with the metallic particle in GIS, AE sensor was designed and simulated by ANSYS, and manufactured as the coupled vibration mode. The resonant frequency of three Coupled AE sensors were as follows ; 147.88 kHz in 8.1 mm$\Phi$ $\times$ 8.1mm, 128.82 kHz in 9.5 mm$\Phi$ $\times$ 9.5mm, 85.22 kHz in 14.3mm$\Phi$ $\times$14.3mm. That frequency is λ/2 resonant frequency. AE sensor of 9.5mm$\Phi$ $\times$9.5mm responded higher than the other coupled vibration mode AE sensor at the partial discharge detection in GIS.

• 전기전자학회논문지
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• 제19권3호
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• pp.392-399
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• 2015

본 논문에서는 HEVC와 VP9 코덱의 계수 변환 (Transform)을 수행하는 통합형 아키텍쳐를 제안하여 하드웨어 크기를 줄이고자 한다. 제안하는 아키텍쳐는 HEVC $4{\times}4$ IDCT, HEVC $4{\times}4$ IDST, VP9 $4{\times}4$ IDCT, VP9 $4{\times}4$ IADST를 통합 하드웨어에서 처리가 가능하다. HEVC $4{\times}4$ IDCT와 VP9 $4{\times}4$ IDCT는 계수의 스케일만 다를 뿐 동일한 IDCT 연산을 사용하며, 마찬가지로 HEVC $4{\times}4$ IDST와 VP9 $4{\times}4$ IADST도 계수의 스케일만 다를 뿐 동일한 IDST 연산을 사용한다. 더욱이 IDCT 연산과 IDST 연산에는 상당히 많은 유사점이 있어 일부 하드웨어를 공동으로 사용할 수 있다. 따라서 제안하는 하드웨어는 4가지 연산에 대해 곱셈기의 계수는 각각 다르지만 버터플라이 덧셈기등은 공통으로 사용하여 통합적으로 수행한다. 0.18um 공정에서 합성했을 때 게이트 수가 약 6,679 게이트로 기존 아키텍처 대비 25.3% 감소함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 춘계학술대회 논문집
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• pp.188-193
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• 1997

ZnO thin film had been deposited on the glass 7r sputtering method, and investigated by electrical and structural properties. When the rf power was 188W and sputtering pressure was 1$\times$10$^{-3}$ Torr at room temperature, Al-doped ZnO thin film had the lowest resistivity(1$\times$10$^{-4}$ $\Omega$.cm), and then carrier concentration and Hall mobility were 6.27$\times$10$^{20}$ cm$^{-3}$ and 22.04$\textrm{cm}^2$/V.s, respectively. And undoped ZnO thin film had about 10$^{14}$ $\Omega$.cm resistivity when oxygen content was 10% or more at room temperature. The surface morphology of ZnO thin film observed by SEM was overall uniform when oxygen content was 50% below and sputtering pressure was 1.0$\times$10$^{-1}$ Torr.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.377-380
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• 2001

The BST thin films to composite (Ba$\sub$x/Sr$\sub$l-x/)TiO$_3$ using sol-gel method were fabricated on Pt/Ti/SiO$_2$/Si substrate. The thin film capacitor to be ferroelectric materials was investigated by structural and electrical properties. BST solution was composited by moi ratio, and then spin-coated (from 3 times to 5 times coating on Pt/SiO$_2$/Si substrate. Thickness of BST ceramics thin films are about 2600∼2800[${\AA}$] in 3 times deposition. The property of leakage current was stable when the applied voltage was 3[V]. Leakage current of 3 times coated BST thin film was 10$\^$-9/∼10$\^$-11/[A] at 0∼3[V].

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.753-758
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• 2003

Ti films were deposited onto 100${\times}$100 mm alumina substrates using dc magnetron sputtering under the following conditions; substrate temperature of R.T～400 $^{\circ}C$, annealing temperature of 100～400 $^{\circ}C$, and sputtering gas pressure of 4${\times}$10$^{-3}$ Torr～4${\times}$10$^{-2}$ Torr. And the films were examined by X-ray diffraction analysis (XRD), scanning electron microscopy(SEM) and 4-point measurement system. The best electrical and structural properties was obtained by substrate temperature of ～200 $^{\circ}C$, target-substrate distance of ～14 cm and sputtering pressure of ～1${\times}$10$^{-2}$ Torr. Also at that condition the most excellent adhesion was observed.

• 대한전자공학회논문지SD
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• 제47권8호
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• pp.47-55
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• 2010

본 논문에서는 고해상도 저전력 SAR 타입 ADC(아날로그 디지털 변환기)의 면적을 획기적으로 줄이기 위해서 역 다중화기 (Demultiplexer)와 카운터 (Counter)를 이용하는 타이밍 레지스터 (Timing register) 구조를 제안하였다. 전통적으로 사용되는 쉬프트 레지스터에 기반을 둔 타이밍 레지스터 구조는 해상도가 증가될수록 면적이 급격하게 증가하고, 또한 잡음의 원인이 되는 디지털 소비 전력도 증가되는 반면, 제안하는 구조는 해상도 증가에 따른 에러 보정 회로의 면적과 소비 전력 증가를 줄일 수 있다. 0.18 um CMOS 공정을 이용하여 제작하였으며, 제안한 타이밍 레지스터 구조를 이용하여, 기존 구조 대비 5.4배의 면적 감소와 디지털 전력 최소화의 효과를 얻을 수 있었다. 설계한 12 비트 SAR ADC는 11 비트의 유효 비트 (ENOB), 2 mW (기준전압 생성 블록 포함)의 소비전력과 1 MSPS의 변환 속도를 보였으며, 레이아웃 면적은 $1mm{\times}1mm$ 이었다.