• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.183-186
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• 2015

This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.357-359
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• 2018

최근 메모리 반도체 시장은 SD(Secure Digital) 메모리 카드, SSD(Solid State Drive)등의 보급률 증가로 메모리 반도체의 시장이 대규모로 증가하고 있다. 메모리 반도체는 개인용 컴퓨터 뿐만 아니라 스마프폰, 테플릿 PC, 교육용 임베디드 보드 등 다양한 산업에서 이용 되고 있다. 또한 메모리 반도체 생산 업체가 대규모로 메모리 반도체 산업에 투자하면서 메모리 반도체 시장은 대규모로 성장되었다. 플래시 메모리는 크게 NAND-Type과 NOR-Type으로 나뉘며 플로팅 게이트 셀의 전압의 따라 SLC(Single Level Cell)과 MLC(Multi Level Cell) 그리고 TLC(Triple Level Cell)로 구분 된다. SLC 및 MLC NAND-Type 플래시 메모리는 많은 연구가 진행되고 이용되고 있지만, TLC NAND-Tpye 플래시 메모리는 많은 연구가 진행되고 있지 않다. 본 논문에서는 기존에 제안된 SLC 및 MLC NAND-Type 플래시 메모리에서 제안된 큐브 패턴을 TLC NAND-Type 플래시 메모리에서 적용 가능한 큐브 패턴 및 알고리즘을 제안한다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.44-52
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• 2002

Since memory technology has been developed fast, test complexity and test time have been increased simultaneously. In practice, March algorithms are used widely for detecting various faults. However, March algorithms cannot detect NPSFs(Neighborhood Pattern Sensitive Faults) which must be considered for DRAMs. This paper proposes an effective algorithm for high fault coverage by modifying the conventional March algorithms.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.4
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• pp.456-462
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• 2008

The classification is that a new data is classified into one of given classes and is one of the most generally used data mining techniques. Memory-Based Reasoning (MBR) is a reasoning method for classification problem. MBR simply keeps many patterns which are represented by original vector form of features in memory without rules for reasoning, and uses a distance function to classify a test pattern. If training patterns grows in MBR, as well as size of memory great the calculation amount for reasoning much have. NGE, FPA, and RPA methods are well-known MBR algorithms, which are proven to show satisfactory performance, but those have serious problems for memory usage and lengthy computation. In this paper, we propose DPA (Dynamic Partition Averaging) algorithm. it chooses partition points by calculating GINI-Index in the entire pattern space, and partitions the entire pattern space dynamically. If classes that are included to a partition are unique, it generates a representative pattern from partition, unless partitions relevant partitions repeatedly by same method. The proposed method has been successfully shown to exhibit comparable performance to k-NN with a lot less number of patterns and better result than EACH system which implements the NGE theory and FPA, and RPA.

• The Journal of the Acoustical Society of Korea
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• v.3 no.1
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• pp.25-35
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• 1984

This paper analysis the Dynamic Time Warping algorithms for time normalization of speech pattern and discusses the Dynamic Programming algorithm for spoken Korean isolated digits recognition. In the DP matching, feature vectors of the reference and test pattern are consisted of first three formant frequencies extracted by power spectrum density estimation algorithm of the ARMA model. The major differences in the various DTW algorithms include the global path constrains, the local continuity constraints on the path, and the distance weighting/normalization used to give the overall minimum distance. The performance criterias to evaluate these DP algorithms are memory requirement, speed of implementation, and recognition accuracy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.327-334
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• 1991

This paper proposes an efficient method of implementing the generalized Hough transform (GHT), which has been hindered by an excessive computing load and a large memory requirement. The conventional algorithm requires a parameter space of 4 dimensions in detection a rotated, scaled, and translated object in an input image. Prior to the application of GHT to the input image, the proposed method determines the angle of rotation and the scaling factor of the test image using the proportion of the edge components between the reference image and test image. With the rotation angle and the scaling factor already determined, the parameter spaceis to be reduced to a simple array of 2 dimensions by applying the unit GHT only one time. The experiments with the image of airplanes reveal that both of the computing time and the requires memory size are reduced by 95 percent, without any degradatationof accuracy, compared with the conventional GHT algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.136-139
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

• Korean Journal of Cognitive Science
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• v.19 no.4
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• pp.369-396
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• 2008

The purpose of this article is to investigate the effect of visual working memory, the types and contents of graphic annotations on English learning. The participants of the experiments were 5th and 6th graders. The result showed that animation was effective only in the word test for children with large visual working memory, whereas text-only-annotation yielded better performance in the comprehension test in Experiment 1. The effect of relevance of animations was tested in Experiment 2. Context-relevant-animations yielded better comprehension than the animations denoting the typical meaning, whereas the opposite pattern was reported in the word test. The result of the two experiments was interpreted in terms of cognitive load theory and the generative theory of multimedia learning.