• Title/Summary/Keyword: Test Access Port

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Effects of EMLA Cream Application on Pain Perception and Pain Response of Children with Cancer During Implanted Venous Access Port Needle Insertion (EMLA크림 도포가 소아암환자의 피하매몰 중심정맥포트 바늘삽입 시 통증인지와 통증반응에 미치는 영향)

  • Seo, Hyun-Young;Kim, Young-Hae
    • Child Health Nursing Research
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    • v.22 no.1
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    • pp.21-28
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    • 2016
  • Purpose: The purpose of this study was to identify effects of EMLA (Eutectic Mixture of Local Anesthetics) cream application on pain perception and pain response during insertion of implanted venous access port needle in children with cancer. Methods: From December 2010 to August 2011, at U university hospital, 20 patients scheduled for implanted venous access port needle insertion were recruited, and randomly assigned to receive either EMLA or a placebo cream 1 hour before the implanted venous access port needle insertion. While conducting needle insertion, changes in pulse and oxygen saturation on the pulse oxymeter monitor were measured and pain behavior reaction was also measured during needle insertion in the treatment room. After conducting needle insertion, self-reported pain reaction, and mothers' perception of the children's pain reaction were measured. Collected data were statistically processed using SPSS version 17.0 for Windows, and analyzed using descriptive statistics, t-test. Results: Children's self-reported degree of pain, degree of pain as perceived by mothers and pain behavior reaction decreased significantly in the EMLA application group compared with the placebo group. Conclusion: Findings indicate that application of EMLA cream is effective in relieving pain in these children during implanted venous access port needle insertion.

Preceding Instruction Decoding Module(PIDM) for Test Performance Enhancement of JTAG based Systems (JTAG 기반 테스트의 성능향상을 위한 PIDM(Preceding Instruction Decoding Module)

  • 윤연상;김승열;권순열;박진섭;김용대;유영갑
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.85-92
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    • 2004
  • A design of a preceding instruction decoding module(PIDM) is proposed aiming at performance enhancement of JTAG-based test complying to the IEEE 1149.1 standard. The PIDM minimizes the number of clocks by performing test access port(TAP) instruction decoding process prior to the execution of TAP-controlled test activities. The scheme allows the generation of signals such as test mode select(TMS) inside of a target system. The design employing PIDM demonstrates 15% performance enhancement with simulation of a CORDIC processor and 48% reduction of the TAP-controller's circuit size with respect to the conventional design of a non-PIDM version.

A Design of New Real Time Monitoring Embedded Controller using Boundary Scan Architecture (경계 주사 구조를 이용한 새로운 실시간 모니터링 실장 제어기 설계)

  • 박세현
    • Journal of Korea Multimedia Society
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    • v.4 no.6
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    • pp.570-578
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    • 2001
  • Boundary scan architecture test methodology was introduced to facilitate the testing of complex printed circuit board. The boundary scan architecture has a tremendous potential for real time monitoring of the operational status of a system without interference of normal system operation. In this paper, a new type of embedded controller for real time monitoring of the operational status of a system is proposed and designed by using boundary scan architecture. The proposed real time monitoring embedded controller consists of test access port controller and an embedded controller proposed real time monitoring embedded controller using boundary scan architecture can save the hard-wire resource and can easily interface with boundary scan architecture chip. Experimental results show that the real time monitoring using proposed embedded controller is more effective then the real time monitoring using host computer.

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IEEE 1500 Wrapper and Test Control for Low-Cost SoC Test (저비용 SoC 테스트를 위한 IEEE 1500 래퍼 및 테스트 제어)

  • Yi, Hyun-Bean;Kim, Jin-Kyu;Jung, Tae-Jin;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.65-73
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    • 2007
  • This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

A Design and Implementation of WLL RIU RF Receiver for Test-bed (Test-Bed용 WLL 가입자장치 RF수신기 설계 및 제작)

  • 강동균;곽벽렬;김동일
    • Journal of the Korean Institute of Navigation
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    • v.22 no.1
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    • pp.51-54
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    • 1998
  • In this paper, RF receiver for CDMA system which has 10 MHz in the channel bandwidth has been designed and fabricated. The designed and fabricated RF receiver is shown useful in operation and the performance has been confirmed by experiments. The results are to be used for establishment of a broadband CDMA wireless access specification standard for WLL system in 2.3 GHz band.

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Investigation and Testing of Location Systems Using WiFi in Indoor Environments

  • Retscher, Guenther;Mok, Esmond
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.83-88
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    • 2006
  • Many applications in the area of location-based services and personal navigation require nowadays the location determination of a user not only in outdoor environment but also indoor. To locate a person or object in a building, systems that use either infrared, ultrasonic or radio signals, and visible light for optical tracking have been developed. The use of WiFi for location determination has the advantage that no transmitters or receivers have to be installed in the building like in the case of infrared and ultrasonic based location systems. WiFi positioning technology adopts IEEE802.11x standard, by observing the radio signals from access points installed inside a building. These access points can be found nowadays in our daily environment, e.g. in many office buildings, public spaces and in urban areas. The principle of operation of location determination using WiFi signals is based on the measurement of the signal strengths to the surrounding available access points at a mobile terminal (e.g. PDA, notebook PC). An estimate of the location of the terminal is then obtained on the basis of these measurements and a signal propagation model inside the building. The signal propagation model can be obtained using simulations or with prior calibration measurements at known locations in an offline phase. The most common location determination approach is based on signal propagation patterns, namely WiFi fingerprinting. In this paper the underlying technology is briefly reviewed followed by an investigation of two WiFi positioning systems. Testing of the system is performed in two localization test beds, one at the Vienna University of Technology and the second at the Hong Kong Polytechnic University. First test showed that the trajectory of a moving user could be obtained with a standard deviation of about ${\pm}$ 3 m.

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Design and Implementation of eBPF-based Virtual TAP for Inter-VM Traffic Monitoring (가상 네트워크 트래픽 모니터링을 위한 eBPF 기반 Virtual TAP 설계 및 구현)

  • Hong, Jibum;Jeong, Seyeon;Yoo, Jae-Hyung;Hong, James Won-Ki
    • KNOM Review
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    • v.21 no.2
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    • pp.26-34
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    • 2018
  • With the proliferation of cloud computing and services, the internet traffic and the demand for better quality of service are increasing. For this reason, server virtualization and network virtualization technology, which uses the resources of internal servers in the data center more efficiently, is receiving increased attention. However, the existing hardware Test Access Port (TAP) equipment is unfit for deployment in the virtual datapaths configured for server virtualization. Virtual TAP (vTAP), which is a software version of the hardware TAP, overcomes this problem by duplicating packets in a virtual switch. However, implementation of vTAP in a virtual switch has a performance problem because it shares the computing resources of the host machines with virtual switch and other VMs. We propose a vTAP implementation technique based on the extended Berkeley Packet Filter (eBPF), which is a high-speed packet processing technology, and compare its performance with that of the existing vTAP.

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

  • Yi, Hyun-Bean;Song, Jae-Hoon;Park, Sung-Ju
    • ETRI Journal
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    • v.30 no.3
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    • pp.403-411
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    • 2008
  • This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

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An Empirical Study on Evaluating the Value of Port (항만가치의 평가에 관한 연구)

  • 김태균;문성혁;노홍승
    • Journal of Korean Society of Transportation
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    • v.19 no.6
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    • pp.75-87
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    • 2001
  • Inter-port competition is fiercer than in the past because of technological evolution in transport systems : the increasing side of containerships implies only a few calls in three or four ports at each end of the trade and the rest of the traffic being served by smaller feederships. It is therefore essential for big ports to be selected as one of these calls by the main shipowners, consortia and alliances to avoid rmarginalisation. In order to compete effectively, many ports have been obliged to modernise and extend considerably its existing ports or to build new port facilities. With the advent of major environmental legislation around the world, however, amenities such as fish and wildlife, clean air and water, access to the waterfront, and view protection took on greater importance. Ports are now being forced to incorporate environmental considerations into their planning and management functions in order to avoid additional costs or timing delays. The aim of this paper is to analyse the port value by which port comparison(or selection) will be made with HFP(Hierarchical Fuzzy Process) method. This was done by extracting and grouping the evaluation factors of port value by port experts : facility and location factor, logistics service factor environment and amenity factor, city and economic factor, and human and system factor. For empirical test of this method, 6 major ports in Northeast Asia were chosen and analysed. The order of importance for five evaluation factors were 1) facility and location factor 2) logistics service factor 3) human and system factor, 4) city and economic factor, and 5) environment and amenity factor. This means that geographical location and logistics services are still being considered as the most important factor to call the port by port users. even though environment and amenity factor shows relatively low figure. Among 6 major ports, Port of Kobe was ranked the first position in a comprehensive evaluation, while Ports of Busan and Kwangyang were 4th and 5th respectively. This implies that Port of Busan should make much efforts to enhance the existing facilities as well as management system.

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Design and Applications of a Generalized Software-Based GNSS IF Signal Generator

  • Lim, Deok-Won;Park, Chan-Sik;Lee, Sang-Jeong
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.211-215
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    • 2006
  • In this paper, design and applications of a generalized, versatile and customizable IF signal generator that can model the modernized GPS and Galileo signal is given. It generates IF sampled data that can be directly used by a software receiver. Entire constellation of satellites which is independent of satellite-user geometry is easily determined using a real or simulated ephemeris data. Since the IF center frequency, sampling frequency and quantization bit number are user location dependent parameters, their effects are also considered in IF signal generator. The generalized IF signal generator will be very well suited for the development phase of a software receiver due to its versatility. The full access to the sampling frequency, front-end filter definition and ADC parameters also offers a great opportunity for cost-effective analysis of tracking loops and error mitigation techniques at the receiver level. Interference sources can be easily added to the generator to simulate specific environments. This software IF signal generator can also be used to feed a multi-frequency multi-system software receiver for the prototyping of a combined GPS/Galileo receiver. The test result using the generated signals and a real software receiver shows the effectiveness of the implemented IF signal generator.

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