• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.84-91
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• 2002

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.9-17
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• 1999

In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.1 s.94
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• pp.150-160
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• 1999

본 논문은 ‘파트 1’에 그 기초를 두었으며, 실제 실험 상황에의 응용예를 들었다. 보편적인 ‘이중-우물 위치 진동기(double-well potential vibrator)'를 외부 공기압 감쇠기를 장치할 수 있도록 수정하였다. 감쇠는 높음 또는 낮음 으로 조정할 수 있도록 하였다. 이 실험계는 주기운동부터 카오스 운동까지 다양한 동적 특성을 보여준다. 힘-위상(Force-Stare Mapping) 방법이 선형상태 및 카오스상태에 응용되었으며, 특히 감쇠의 높고 낮음의 파악에 그 중점을 두었다. 그리고 , 부분발산지수들(Short term averaged Lyapunov exponents)의 합이 또한 감쇠를 파악함과 동시에 높은 감쇠에서 낮은 감쇠로의 변화를 감시할 수 있음을 보였다. 이 두가지 방법들을 비교하였으며 논하였다.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.15-24
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result. it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB.

• The Bulletin of The Korean Astronomical Society
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• v.41 no.1
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• pp.70.4-71
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• 2016

The links between super-massive black hole masses and their host galaxy properties are observed, indicating that black hole growth and host galaxy evolution are closely related. Reverberation mapping, which uses the time delay from the central black hole to broad line regions, is one of the best methods to estimate masses of black holes of active galactic nuclei (AGNs). However, only masses of about 50 black holes have been determined in reverberation mapping studies so far, and most of them are limited to optical luminosities below 10^45 erg/s due to the challenges of long-term time domain observations in both photometry and spectroscopy. In this project, we expand reverberation mapping samples to higher luminosities of > 10^44.5 erg/s at 0.1 < z < 0.35, that have expected time lags of 40 - 250 light days. Photometric (using LOAO 1-m and MDM 1.3-m) and spectroscopic (using MDM 2.4-m and Lick 3-m) monitoring campaigns are being conducted for a 3 year duration and 20 day cadence. Precedent photometric observations in 2015B show some targets with variability and follow-up spectroscopic observations are on-going. In this presentation, we introduce our project, present reverberation mapping simulation results, and preliminary results on photometry. These reverberation mapping masses of relatively high luminous AGNs will provide a strong constraint on black hole mass calibration, e.g., the single-epoch mass estimation.

• Bulletin of the Korean Mathematical Society
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• v.56 no.4
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• pp.1077-1097
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• 2019

Let M be a finitely generated module over a regular local ring (R, n). We will fix an n-stable filtration for M and show that the minimal free resolution of M can be obtained from any filtered free resolution of M by zero and negative consecutive cancellations. This result is analogous to [10, Theorem 3.1] in the more general context of filtered free resolutions. Taking advantage of this generality, we will study resolutions obtained by the mapping cone technique and find a sufficient condition for the minimality of such resolutions. Next, we give another application in the graded setting. We show that for a monomial order ${\sigma}$, Betti numbers of I are obtained from those of $LT_{\sigma}(I)$ by so-called zero ${\sigma}$-consecutive cancellations. This provides a stronger version of the well-known cancellation "cancellation principle" between the resolution of a graded ideal and that of its leading term ideal, in terms of filtrations defined by monomial orders.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.35-46
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm. a given logic equation is constructed as the DAG type. then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also. after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within Cl.B. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time much more than the TMCPLD.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.407-409
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• 1998

This paper deals with temporal-difference learning that is a method for approximating long-term future cost as a function of current state in knowlege-poor environment, a function approximator is used to approximate the mapping from state to future cost, a linear function approximator is limited because mapping from state to future cost has a nonlinear characteristic, so a nonlinear function approximator is used to approximate the mapping from state to future cost in this paper, and that TD learning using a nonlinear function approximator is stable is proved.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.75-77
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• 2003

The spatial distribution of snow cover area is a crucial input to models of hydrology and climate in alpine and other seasonally snow covered areas.The objective in our study is to develop a rapidly automatic and high accuracy snow cover mapping algorithm applicable for the Tibetan Plateau which is the most sensitive about climatic change. Monitoring regional snow extent reqires higher temoral frequency-moderate spatial resolution imagery.Our algorithm is based AVHRR and MODIS data and will provide long-term fraction snow cover area map.We present here a technique is based on the multiple endmembers approach and by taking advantages of current approaches, we developed a technique for automatic selection of local reference spectral endmembers.

• Journal of Forest and Environmental Science
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• v.29 no.4
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• pp.307-313
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• 2013

Forest Survey consists of road survey, topographic survey, tree mapping survey, stream survey and also ridge survey. Information from forest survey is important and become essential in preparing base map to be used for forest harvesting planning and control. With the current technologies technique of data processing and mapping from traditionally hand drawn method had shifted to a computer system particularly the use of Computer Aided Design (CAD). This gives great advantages to the forest managers and logging operators. However data processing and mapping duration could be further reduced by integrating CAD with other established software such as Microsoft Excel. This time study to show that there is significance difference in term of duration for data processing and efficiency using AutoCAD in combination with Microsoft Excel program as compare to the use of AutoCAD program alone. From the study, it shows that the integration of AutoCAD and Microsoft Excel is able to reduce 70% of duration for data processing and mapping as compared to the use of AutoCAD program alone.