• Journal of Navigation and Port Research
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• v.36 no.8
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• pp.637-641
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• 2012

In this paper, the method that reduce a computation time by optimizing computation process is proposed to realize low-power underwater acoustic communication system. At first, dependency of decision delay on tap length of linear equalizer was investigated. Variance is calculated based on this result, and the optimal decision delay bound is estimated. In addition to decide optimal tap length with decision delay, we extracted the MSE(Mean Square Error) graph. From the graph, we obtained variance value of the MSE-decision delay, and estimated the optimum decision delay range from the variance value. Also, using the extracted optimal parameters, we performed a simulation. According to the result, the simulation employing optimal tap length, which is only 40% of maximum tap length, showed a satisfactory performance comparable to simulation employing maximum tap length. We verified that the proposed method has 33% lower tap length than maximal tap length via sea trial.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.293-296
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• 2000

In this paper, we designed a 192-tap echo canceller for a modem using VHDL. To evaluate errors, we used adaptive algorithm. We adopted pipeline technique and realized delay-taps with RAMs. We simulated this design using Altera MAX+PLUS II.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.859-862
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• 1999

We designed a 128-tap FIR filter for a modem which complies with ITU-T V.32. We adopted pipeline technique and realized delay-taps with two ring-buffers. The multiplier in this filter carries out 2's complement fixed-point multiplication of 14bit $\times$ 16bit. The designed filter is expected to operate at 50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.728-734
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• 2001

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.

• International Journal of Computer Science & Network Security
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• v.23 no.7
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• pp.1-8
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• 2023

An Orthogonal Frequency Division Multiplexing (OFDM) based wireless communication system has drawn wide attention for its high transmission rate and high spectrum efficiency in not only radio but also Underwater Acoustic (UWA) applications. Because of the narrow sub-carrier spacing of OFDM, orthogonality between sub-carriers is easily affected by Doppler effect caused by the movement of transmitter or receiver. Previously, Doppler compensation signal processing algorithm for Desired propagation path was proposed. However, other Doppler shifts caused by delayed Undesired signal arriving from different directions cannot be perfectly compensated. Then Receiver Bit Error Rate (BER) is degraded by Inter-Carrier-Interference (ICI) caused in the case of Multi-path Doppler channel. To mitigate the ICI effect, a modified Delay and Doppler Profiler (mDDP), which estimates not only attenuation, relative delay and Doppler shift but also sampling clock shift of each multi-path component, is proposed. Based on the outputs of mDDP, an ICI canceling multi-tap equalizer is also proposed. Computer simulated performances of one-tap equalizer with the conventional Time domain linear interpolated Channel Transfer Function (CTF) estimator, multi-tap equalizer based on mDDP are compared. According to the simulation results, BER improvement has been observed. Especially, in the condition of 16QAM modulation, transmitting vessel speed of 6m/s, two-path multipath channel with direct path and ocean surface reflection path; more than one order of magnitude BER reduction has been observed at CNR=30dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2151-2156
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• 2006

Beamforming for underwater acoustic communication (UAC) is affected by the broadband feature of UAC signal, which has relatively low currier frequency as compared to the signal bandwidth. The narrow-band assumption does not hold good in UAC. In this paper, we discuss a broadband FIR beamformer for UAC using the baseband equivalent way signal model. We consider the broadband FIR beamformer for QPSK UAC with carrier frequency 25kHz and symbol rate 5kHz. Array geometry is a uniform linear way with 8 omni-directional elements and sensor spacing is the half of the carrier wavelength. The simulation results show that the broadband n beamformer achieves nearly optimum signal to interference and noise ratio (SINR) and outperforms the conventional narrowband beamformer by SINR 0.5dB when two-tap FIR filter is employed at each sensor and the inter-tap delay is a quarter of the symbol interval. The broadband FIR beamformer performance is more degraded as the FIR filter length is increased above a certain value. If the inter-tap delay is not greater than half of the symbol period, SINR performance does not depend on the inter-tap delay. More training period is required when the inter-tap delay is same as the symbol period.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.496-500
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• 2003

In This paper, a pole-zero optimized design method for multi-layed planar interdigital stripeline linear group delay bandpass filter with tap input port is presented. As a design example, a four-pole group delay filter with center frequency of 2.14GHz, bandwidth of 160MHz, and group delay variation of ${\pm}0.1nS$ for LTCC technology or multilayerd PCB technology is designed. In the design process, as well the whole structure is not necessary to be simulated, and within three times of optimizing process we have good result as well. This design method could be useful for controlling error correction of manufacturing process as well as design stage.