• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.256-256
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• 2008

We report epitaxial growth of ZnO thin films on (100) single-crystalline $LaAlO_3$ (LAO) substrates using pulsed laser deposition (PLD) at different substrate temperatures (400~$800^{\circ}C$). The structural and electrical properties of the films have been investigated by means of X-ray diffraction (XRD), atomic force microscope (AFM), transmission line method (TLM). The poly-crystalline of $\alpha$- and c-axis oriented ZnO film was formed at lower deposition temperature ($T_s$) of $400^{\circ}C$. At higher $T_s$, however, the films exhibit single-crystalline of $\alpha$-axis orientation represented by ZnO[$\bar{1}11$ || LAO <001>. The electrical properties of ZnO thin films depend upon their crystalline orientation, showing lower electrical resistivity values for $\alpha$-axis oriented ZnO films.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.237-240
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• 2005

This paper propose an novel CAVLC architcture for H.264 and designed the CAVLC module which can be used in AMBA based design. This designed module can be operated in 420 cycle for one-macroblock and support both long-start code method using Annex B.1 and RTP. To verify the CAVLC architecture, we developed the reference C from JM8.5 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 54MHz clock system, and has 14096 gate counts using Hynix 0.35 um TLM process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.449-454
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• 2002

The use of a thin film of indium between the ITO and the $n^+-lnP$ contact layers for InP/InGaAs HPTs was studied without degrading its excellent optical transmittance properties. $ITO/n^+-lnP$ ohmic contact was successfully achieved by the deposition of indium and annealing. The specific contact resistance of about $6.6{\times}10^{-4}\Omega\textrm{cm}^2$ was measured by use of the transmission line method (TLM). However, as the thermal annealing was just performed to $ITO/n^+-lnP$ contact without the deposition of indium between ITO and $n^+-lnP$, it exhibited Schottky characteristics. In the applications, the DC characteristics of InP/InGaAs HPTs with ITO emitter contacts was compared with those of InP/InGaAs HBTs with the opaque emitter contacts.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.50-57
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• 2011

Conventional bus system architectures are composed of several components such as master, arbiter, decoder and slave modules. The arbiter plays a role in bus arbitration according to the selected arbitration method, since several masters cannot use the bus concurrently. Typical priority strategies used in high performance arbiters include static priority, round robin, TDMA and lottery. Typical arbitration algorithms always consider the bus priority primarily, while the bus utilization is always ignored. In this paper, we propose an arbitration method using bus utilization for the operating block of each master. We verify the performance compared with the other arbitration methods through the TLM(Transaction Level Model). Based on the performance verification, the conventional fixed priority and round-robin arbitration methods cannot set the bus utilization. Whereas, in the case of the conventional TDMA and lottery arbitration methods, more than 100,000 cycles of bus utilization can be set by the user, exhibiting differences of actual bus utilization up to 50% and 70%, respectively. On the other hand, we confirm that for the proposed arbitration method, the matched bus utilization set by the user was above 99% using approximately 1,000 cycles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.57-64
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• 2008

In this paper, we propose a system-level simulator for the performance analysis of a Solid-State Disk (SSD) in PC environment by using TLM (Transaction Level Modeling) method. Our method provides quantitative analysis for a variety of architectural choices of PC system as well as SSD. Also, it drastically reduces the analysis time compared to the conventional RTL (Register Transfer Level) modeling method. To show the effectiveness of the proposed simulator, we performed several explorations of PC architecture as well as SSD. More specifically, we measured the performance impact of the hit rate of a cache buffer which temporarily stores the data from PC. Also, we analyzed the performance variation of SSD for various NAND Flash memories which show different response time with our simulator. These experimental results show that our simulator can be effectively utilized for the architecture exploration of SSD as well as PC.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.43-50
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• 2016

NAND flash based storage devices adopts multi-channel and multi-way architecture to improve performance using parallel operation of multiple NAND devices. However, multiple NAND devices consume higher current and peak power overlap problem influences on the system stability and data reliability. In this paper, current waveform is measured for erase, program and read operations, peak current and model is defined by profiling method, and estimated probability of peak current overlap among NAND devices. Also, system level TLM simulator is developed to analyze peak overlap phenomenon depending on various simulation scenario. In order to remove peak overlapping, token-ring based simple power management method is applied in the simulation experiments. The optimal peak overlap ratio is proposed to minimize performance degradation based on relationship between peak current overlapping and system performance.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.2
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• pp.60-64
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• 2023

In this study, the electrical contact resistance characteristics between graphene and metals, which is one of important factors for the performance of graphene-based devices, were compared. High-quality graphene was synthesized by chemical vapor deposition (CVD) method, and Al, Cu, Ni, and Ti as electrode materials were deposited on the graphene surface with equal thickness of 50 nm. The contact resistances of graphene transferred to SiO₂/Si substrates and metals were measured by the transfer length method (TLM), and the average contact resistances of Al, Cu, Ni, and Ti were found to be 345 Ω, 553 Ω, 110 Ω, and 174 Ω, respectively. It was found that Ni and Ti, which form chemical bonds with graphene, have relatively lower contact resistances compared to Al and Cu, which have physical adsorption properties. The results of this study on the electrical properties between graphene and metals are expected to contribute to the realization of high-performance graphene-based devices including electronics, optoelectronic devices, and sensors by forming low contact resistance with electrodes.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.6
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• pp.885-895
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• 1994

In this paper, we propose the one-Ampere conductor method which is able to calculate the flux distribution conceptually and easily, and the improved winding method which suppresses space harmonics of magnetormotive force and enhances the coefficient of utilization of primary iron core in tubular linear induction motor. We carry out no-load test to verify effectiveness of proposed method and analyze characteristics by finite element method. As a result, performances are improved and propriety of primary iron core is enhanced comparing with conventional model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.197-200
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• 2001

In this letter, we report on the investigation of Ni/Si/Ni Ohmic contacts to n-type 4H-SiC. Ohmic contacts have been formed by a vacuum annealing and $N_2$ gas ambient annealing method at $950^{\circ}C$ for 10 min. The specific contact resistivity ( $\rho_{c}$ ), sheet resistance($R_s$), contact resistance($R_c$), transfer length($L_T$) were calculated from resistance($R_T$) versus contact spacing(d) measurements obtained from 10 TLM(transmission line method) structures. The resulting average values of vacuum annealing sample were $\rho_{c}=3.8{\times}10^{-5}\Omega cm^{3}$, $R_{c}=4.9{\Omega}$, $R_{T}=9.8{\Omega}$ and $L_{T}=15.5{\mu}m$, resulting average values of another sample were $\rho_{c}=2.29{\times}10^{-4}\Omega cm^{3}$, $R_{c}=12.9{\Omega}$ and $R_{T}=25.8{\Omega}$. The physical properties of contacts were examined using X-Ray Diffraction and Auger analysis, there was a uniform intermixing of the Si and Ni, migration of Ni into the SiC.