• ETRI Journal
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• v.30 no.6
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• Journal of Sensor Science and Technology
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• v.15 no.2
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• Proceedings of the KAIS Fall Conference
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• 2009.12a
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• pp.190-193
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• 2009

The most essential element in wireless sensor network is wireless sensor node which collects environmental information and transmits it to the user application systems. Recently, due to the technological advancement, wireless sensor nodes are become smaller, more intelligent and less power consuming. Especially, SoC(System-on-Chip) technology, which unifies the MCU, RF module, memory and other element inside one chip, plays an important part for miniaturization of sensor node, hence reduces the manufacturing expenses. In this paper, we have designed a miniaturized wireless sensor node for wireless sensor network using commercial SoC technology and discussed about some application scenario and additional considerations.

• ETRI Journal
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• v.32 no.4
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2559-2561
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• 2004

This paper proposes the new signal-to-noise ratio(SNR) that is different from the conventional signal-to-noise ratio (SNR) in direct-sequence code-division multiple-access communication system employing offset quadrature phase-shift keying(OQPSK) and using a chip waveform. The conventional SNR value is so different from a real SNR value. Therefore, we propose a new SNR equation approximated to real SNR. The multiple-access interference(MAI) in DS-CDMA communication system has an effect on SNR performance and MAI is concerned with the correlation functions of the chip waveform. For this reason, we considered all possible correlations of chip waveforms. In conclusion, the SNR value of proposed method is enclosed to the real SNR value.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.131-137
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• 2016

In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• The KIPS Transactions:PartA
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• v.13A no.7 s.104
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• pp.589-598
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• 2006

In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.4
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• pp.68-75
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• 2005

This paper presents a new method for the optimization of feed rate in sculptured surface machining. A NC verification model based on Z-map was utilized to obtain chip load according to feed per tooth. This optimization method can regenerate a new NC program with respect to the commanded cutting conditions and the NC program that was generated from CAM system. The regenerated NC program has not only the same data of the ex-NC program but also the updated feed rate in every block. The new NC data can reduce the cutting time and produce precision products with almost even chip load to the feed per tooth. This method can also reduce tool chipping and make constant tool wear.