• ETRI Journal
• /
• v.23 no.3
• /
• pp.138-149
• /
• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.365-368
• /
• 2003

In this Paper, we report a design of Serial ATA Transpor layer. The functionalities of the Serial ATA transport layer are first described on RTL via verilog. The compiled code are then fed to a synthesizer synopsys to get the actual hardware from 0.35$\mu\textrm{m}$ SAMSUNG standard cell library. The designed functionalities of this chip will be verified using test bold with FPGA equipment and ATS2 digital test equipment.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.28-31
• /
• 2003

In this paper, it proposes the efficient iterative decoding stop criterion using the variance value of LLR. It is verifying that the proposal iterative de-coding stop criterion can be reduced the average iterative decoding number. The proposal algorithm md hardware synthesize to use the Synopsys Tool, performance validations perform through the ModelSim.

• Journal of Information Display
• /
• v.2 no.2
• /
• pp.13-21
• /
• 2001

We propose a universal image processor for a-Si TFT LCD of UXGA class that can display the full screen on the LCD panel with low resolution of video sources such as NTSC, VGA, SVGA, XGA, and SXGA by using the proposed interpolation filter. In addition, we propose a real-time contrast controller for image improvement of multi-gray scale image. The operation of the proposed methods has been verified using Synopsys VHDL and computer simulation. Results show that the proposed methods might be suitable for a UXGA LCD controller for real-time image improvement.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.10A
• /
• pp.1598-1603
• /
• 2000

In this paper, an efficient pulse shaping filter architecture for SSB/BPSK-DS/CDMA is proposed. The filter satisfies the specifications in IS-95. The proposed architecture is based on polyphase decomposition and look-up table method. By exploiting the linear phase property of the decomposed filter coefficients, the chip area required for look-up table can be reduced by half compared with the conventional methods. By Synopsys simulations, it is shown that the use of the proposed method can result in reduction in the number of gates by 40%.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.2C
• /
• pp.150-159
• /
• 2002

This paper presents the convergence time, SER(Symbol Error Rate), MSE(Mean Square Error), hardware complexity and step-size(${\mu}$) about various LMS(Least Mean Square) algorithms in FS-DFE(Fractionally Spaced-Decision Feedback Equalize) for Cable Modem based on MCNS(Multimedia Cable Network System) DOCSIS(Data Over Cable Service Interface Specification) v1.0/v1.1 standards. We designed and simulated using ${SPW}^{TM}$ and synthesized using STD90 library through ${SYNOPSYS}^{TM}$. And also, we adopted the time-multiplexed multiplication and tap shared architecture in order to achieve the low hardware complexity. Simulation results show that DS-LMS algorithms[1][3] is the optimum solution about performace and hardware size. in high order QAM applications. Finally, we achieved area saving about 58% using DS-LMS algorithm compare with conventional equalizer architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.93-101
• /
• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.33-38
• /
• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.34-41
• /
• 2011

This paper presents a 24 channel capacitive touch sensing ASIC. This ASIC consists of analog circuit part and digital circuit part. Analog circuits convert user screen touch into electrical signal and digital circuits represent this signal change as digital data. Digital circuit also has an I2C interface for operation parameter reconfiguration from host machine. This interface guarantees the stable operation of the ASIC even against wide operation condition change. This chip is implemented with 0.18 um CMOS process. Its area is about 3 $mm^2$ and power consumption is 5.3mW. A number of EDA tools from Cadence and Synopsys are used for chip design.

• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.80-86
• /
• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.