Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

A Study on a New ESD Protection Circuit with Parasitic PNP BJT Insertion Type with High Robustness Characteristics Based on SCR

SCR 기반 고감내 특성을 갖는 기생 PNP BJT 삽입형 새로운 ESD 보호회로에 관한 연구

  • Chae, Hee-Guk (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Do, Kyoung-Il (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Seo, Jeong-Yun (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Seo, Jeong-Ju (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Koo, Yong-Seo (Dept. of Electronics Engineering, DanKook Unversity)
  • Received : 2018.03.10
  • Accepted : 2018.03.24
  • Published : 2018.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

본 논문에서는 기존 ESD 보호회로인 SCR, LVTSCR 보다 향상된 전기적 특성을 갖는 새로운 PNP 바이폴라 삽입형 ESD 보호회로를 제안한다. 제안된 회로는 기존 SCR에 대비하여 약 9V낮은 8.59V의 트리거 전압을 가지고, 기생 PNP가 하나 더 동작하면서 높은 감내특성을 갖는다. 또한 제안된 ESD 보호회로의 실제 설계 적용을 위해 변수 L을 늘리면서 기생 PNP의 베이스 길이를 늘려 홀딩전압을 증가시켰다. 제안된 소자의 전기적 특성 검증을 위해 Synopsys사의 T-CAD 시뮬레이터를 사용하였다.

Keywords

References

  1. Hyun-Young Kim, "A Study on the Electrical Characteristic of SCR-based Dual-Directional ESD Protection Circuit According to Change of Design Parameters" j.inst.Korean.electr.electron.eng, vol.19, no.2, pp.265-270, 2015.DOI : 10.7471/ikeee.2015.19.2.265
  2. Albert Z. H. Wang, On-Chip ESD Protection for Integrated Circuits 2nd ed, Springer, 2002.
  3. M.D. Ker and C.C. Yen, "Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latch up-Like Failure During System-Level ESD Test," IEEE J . Solid-State Circuits, vol.43, no.11, pp. 2533-2545. 2008.DOI: 10.1109/JSSC.2008.2005451
  4. C. Russ, K. Bock, M. Rasras, I. D. Wolf, G.Groeseneken, and H. E. Maes, "Non-uniform triggering of gg-nMOSs investigated by combined emission microcopy and transmission line pulsing," in Proc. EOS/ESD Symp., pp.177-186, 1998, DOI : 10.1109/EOSESD.1998.737037
  5. J.Y. Lee "Analysis of SCR, MVSCR, LVTSCR With I-V Characteristic and Turn-On-Time," j.inst.Korean.electr.electron.eng, vol.20, no.3, pp.295-398, 2016.DOI: 10.7471/ikeee.2016.20.3.295
  6. O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," EOS/ESD Symp, pp.77-86, 2006, DOI : 10.1109/EOSESD.2006.5256797
  7. V. Vashchenko, A. Concannon, M. ter Beek, P. Hopper, "High holding voltage cascode LVTSCR structures for 5.5-V tolerant ESD protection clamps," IEEE Trans. on Device and Materials Reliability, vol.4, no.2, pp.273-280, 2004.DOI:10.1109/TDMR.2004.826584
  8. A Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol.12, no.1, pp. 21-22, 1991.DOI: 10.1109/55.75685