• Journal of IKEEE
• /
• v.20 no.3
• /
• pp.295-298
• /
• 2016

In this paper, we analysed the properties of the conventional ESD protection devices such as SCR, MVSCR, LVTSCR. The electrical characteristics and the turn-on time properties are simulated by Synopsys T-CAD simulator. As the results, the devices have the holding voltages between 2V and 3V, and the trigger voltage of about 20V with SCR, of about 12V with MVSCR, of about 9V with LVTSCR. The results of the simulation for the turn-on time properties are 2.8ns of SCR, 2.2ns of MVSCR, 2.0ns of LVTSCR. Thus, we prove that LVTSCR has the shortest turn-on time. However, the second breakdown currents(It2) of the devices are 7.7A of SCR, 5.5A of MVSCR, 4A of LVTSCR. This different properties have to be adapted by the operation voltages for I/O Clamps.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.168-173
• /
• 2021

In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.178-179
• /
• 2005

ESD(Electrostatic Discharge) 보호에 응용되는 소자는 ESD가 발생했을 때, 빠르게 턴-온되어 외부로부터 EOS(Electric OverStress)를 차단함으로서 집적회로 내부의 코어를 보호해 주어야 한다. 이러한 기능에 충실한 LVTSCR(Low-Voltage Silicon Controlled Rectifier)은 트리거링 전압을 기존의 SCR보다 낮추어 ESD에 대해 민감한 반응을 할 수 있도록 개선한 소자이다. 그러나 트리거링 전압을 낮추면서 래치업 전압 또한 낮아지는 특성이 trade-off 관계로 맞물려 있어, LVTSCR의 단점인 낮은 래치업 전압을 효과적으로 다루는 것이 큰 이슈가 되고 있다. 본 논문에서는 LVTSCR의 ESD 보호에 대한 응용시 발생 가능한 래치업을 차폐하는 회로적 방법을 제시하였다. 제시된 새로운 구조의 차폐회로는 LVTSCR에서 래치업이 발생했을 때, 천이 전류를 감지하여 래치업이 발생되는 소자에 대한 전원을 스스로 차폐시켜 래치업에 대한 안정성을 시뮬레이션으로 검증하였다.

• Journal of IKEEE
• /
• v.9 no.2 s.17
• /
• pp.161-169
• /
• 2005

This paper presents the new structural Low voltage LVTSCR and TWSCR ESD protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. And the LVTSCR has the triggering voltage of 9V, current of 7mA and can pass below 0.8KV (150mA/um). The triggering voltage of the Triple-well SCR measured to 6V and the current is 40mA. By the substrate and gate bias, the triggering voltage is lowered down to $4{\sim}5.5V$.

• Journal of IKEEE
• /
• v.22 no.3
• /
• pp.836-841
• /
• 2018

In this paper, This paper is based on the conventional ESD protection circuits SCR and LVTSCR. Also, the SCR-based ESD protection circuit, which is different from the conventional structure, is presented and tested for variations in the trigger voltage and holding voltage. Due to the insertion of additional N +, P + regions, the newly added SCR-based protection circuit have improved electrical characteristics. To discuss the electrical characteristics of the proposed circuit, Synopsys T-CAD simulation data was shown.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.890-894
• /
• 2020

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

• Journal of IKEEE
• /
• v.20 no.4
• /
• pp.361-366
• /
• 2016

This paper presents the ESD protection circuit with improved electrical characteristic and area efficiency. The proposed ESD protection circuit has higher holding voltage and lower trigger voltage characteristics than the 3-Stacking LVTSCR. In addition, it has only two stages and has improved Ron characteristics due to short discharge path of ESD current. We analyzed the electrical characteristics of the proposed ESD protection circuit by TCAD simulator. The proposed ESD protection circuit has a small area of about 35% compared with 3-Stacking LVTSCR, The proposed circuit is designed to have improved latch-up immunity by setting the effective base length of two NPN parasitic bipolar transistors as a variable.

• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.80-86
• /
• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

• Journal of IKEEE
• /
• v.23 no.1
• /
• pp.338-341
• /
• 2019

In this paper, we propose a novel ESD device with improved characteristics of LVTSCR, which is a representative ESD protection device, and verify the N-stack technology for design optimized for each required voltage of a specific application. The characteristics of the holding voltage and the trigger voltage, which are the main parameters, are examined and the temperature characteristic, which is an indicator of the tolerance characteristic, is also verified. well region and a parasitic NPN to form a series-connected structure. We used synopsys' T-cad simulation tool for characterization.

• Journal of IKEEE
• /
• v.26 no.3
• /
• pp.520-523
• /
• 2022

In this paper, an ESD protection device with a simpler structure than the existing ESD protection device is proposed. The proposed new structure operates an additional NPN parasitic bipolar transistor by adding an N+ diffusion region and connecting it to the bridge region, thereby lowering the current gain. As a result, it was confirmed that the proposed ESD protection device has a trigger voltage of 10.8V and a holding voltage of 6.1V. It is expected to have reliability for 5V applications and is expected to have high tolerance characteristics.