• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.2051-2054
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• 2004

This paper proposes a more accurate task level energy measurement technique for high speed microprocessors. The technique is based on the relationship of the amount of current consumed by the microprocessor and the pulse width of the power supply controller chip, employed in the synchronous buck DC-DC converter in the microprocessor's power supply. The accuracy of the measurement is accomplished by measuring variation in pulse width in each power supply cycle. The major advantage of this technique is that its accuracy does not depend on the operating frequency of the microprocessor. To prove the proposed technique, we implemented the measurement unit of the microprocessor energy meter using an FPGA chip operating at 50 MHz. Both static and dynamic load measurement are tested in order to obtain some behaviours. Moreover, various commercially available mainboards which employ synchronous buck regulators at 200 KHz switching frequency, were measured. The results agree with previous works with better accuracy at higher operating frequency.

• Journal of Power Electronics
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• v.9 no.3
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• pp.410-417
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• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• Journal of Power Electronics
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• v.16 no.1
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• pp.74-83
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• 2016

A new family of zero-voltage-transition converters with synchronous rectification is introduced in this study. Soft switching condition for all the converter operating points is provided in the proposed converters. The reverse recovery losses of the rectifier switch body diode are also eliminated. In comparison with the main switch voltage stress, the auxiliary switch voltage stress is reduced significantly. The auxiliary switch does not need the floating gate drive. The auxiliary inductor is coupled with the main converter inductor, and the leakage inductor is used as the resonance inductor. Thus, all inductors of the proposed converter can be implemented on a single core. The other features of the proposed converters include no extra voltage and current stresses on the main converter semiconductor elements. Theoretical analysis for a synchronous buck converter is presented in detail, and the validity of the theoretical analysis is justified with the experimental results of a prototype buck converter with 180 W and 80 V to 30 V.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1445-1453
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• 2017

In this study, a new zero-voltage transition (ZVT) buck converter with coupled inductor using a synchronous rectifier and a lossless clamp circuit is proposed. The regular buck converter with tapped inductor has extended duty cycle for high step-down applications. However, the leakage inductance of the coupled inductor produced considerable voltage spikes across the switch. A lossless clamp circuit is used in the proposed converter to overcome this problem. The freewheeling diode was replaced with a synchronous rectifier to reduce conduction losses in the proposed converter. ZVT conditions at turn-on and turn-off instants were provided for the main switch. The synchronous rectifier switch turned on under zero-voltage switching, and the auxiliary switch turn-on and turn-off were under zero-current condition. Experimental results of a 100 W-100 kHz prototype are provided to justify the validity of the theoretical analysis. Moreover, the conducted electromagnetic interference of the proposed converter is measured and compared with its hard-switching counterpart.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.175-177
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• 2007

An analysis on a passive current sharing characteristics of a multi-phase synchronous buck converter is presented. The passive current sharing method is simple but its characteristics depend on the converter equivalent resistance and PWM uniformity. In this paper, the load sharing and power consumption of the passive current sharing system for the converter equivalent resistance and duty ratio inequalities are investigated through the simulation and experiment.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1069-1070
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• 2008

This paper presents a high efficient two-stage interleaved synchronous buck CMOS DC-DC converter. The proposed circuit has a fixed duty cycle as 0.5 by an added buck converter. And it causes the best ripple cancelation of the output current ripple. The proposed circuit was simulated by HSPICE with a standard CMOS $0.35{\mu}m$ process parameter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.312-323
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• 2017

This paper introduces the bidirectional dc-dc converter design case study, which employs silicon-carbide (SiC) MOSFETs for battery energy storage system (BESS). This converter topology is selected as bidirectional synchronous buck converter, which is composed of a half bridge converter, an inductor, and a capacitor, where the converter has less conduction loss than that of a unidirectional buck and boost converter, and to improve the converter efficiency, both the power stage design and power conversion architecture are described in detail. The conduction and switching losses are compared among three different SiC devices in this paper. In addition, the thermal analysis using Maxwell software of each switching device supports the loss analyses, in which both the 2 kW prototype analyses and experimental results show very good agreement.

• Journal of Power Electronics
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• v.17 no.3
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• pp.601-609
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• 2017

Gallium nitride (GaN) power switching devices are promising candidates for high switching frequency and high efficiency power conversion due to their fast switching, low on-state resistance, and high-temperature operation capability. In order to facilitate the use of these new devices better, it is required to investigate the device characteristics and performance in detail preferably by comparing with various conventional silicon (Si) devices. This paper presents a comprehensive study of GaN high electron mobility transistor (HEMT) based non-isolated point-of-load (POL) synchronous buck converter operating at 2.7 MHz with a high step-down ratio (24 V to 3.3 V). The characteristics and performance of GaN HEMT and three different Si devices are analytically investigated and the optimal operating point for GaN HEMT is discussed. Zero-voltage switching (ZVS) is implemented to minimize switching loss in high switching frequency operation. The prototype circuit and experimental data support the validity of analytical and simulation results.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.17-18
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• 2010

최근 전력변환기의 효율 증대를 위한 소프트 스위칭 및 동기형 DC/DC 컨버터에 대한 연구가 활발히 진행되고 있다. 따라서 본 논문에서는 동기형 Buck-Converter를 이용한 Full-Bridge DC/DC 컨버터의 ZVS 기법에 대하여 연구 하였으며, 제안된 방식의 타당성을 검증하기 위해 Psim을 이용한 시뮬레이션을 행하였다.