• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.277-279
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• 2005

Recently, due to the increase of power conversion devices and nonlinear loads with the development of information, communication and control technologies, the instantaneous minute interruption factors such as voltage & current harmonics, surge occurring frequency, instantaneous voltage variation, voltage unbalance, flicker etc. have greatly threatened the power quality, and the deterioration of electric power facilities and the functional error of controllers are increasing. As such an instantaneous minute interruption appears to be small and local, accurate evaluation with measurement is difficult and total analysis system is required through a wide range of power quality effect analysis such as the simultaneous measurement on various power supply phenomena and the analysis on the interrelation with system loads. Most of conventional power quality diagnosis equipments have beer developed and applied, which were able to measure the stability rate of frequency, the stability rate of voltage, the electricity-failure duration etc, However, they were insufficient to analyze the system present situation, understand the cause of the failure occurred by the problem of power quality and analyze out the phenomena. Accordingly, this study will address the development of the system for a wide range of power quality diagnosis over the present level, the system for supporting the determination such as the analysis on risk factors, failure mode and impact, the system for harmonic evaluation based on international standards(IEC 61000 Series) and the total power quality diagnosis network & system with the extension and openness as a local and national-scale broadband power quality diagnosis system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.27-36
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• 2005

This paper presents an area-efficient architecture to implement the high-speed Reed-Solomon(RS) decoder, which is used in a variety of communication systems such as wireless and very high-speed optical communications. We present the new pipelined-recursive Modified Euclidean(PrME) architecture to achieve high-throughput rate and reducing hardware-complexity using folding technique. The proposed pipelined recursive architecture can reduce the hardware complexity about 80$\%$ compared to the conventional systolic-array and fully-parallel architecture. The proposed RS decoder has been designed and implemented with the 0.13um CMOS technology in a supply voltage of 1.2 V. The result show that total number of gate is 393 K and it has a data processing rate of S Gbits/s at clock frequency of 625 MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of Convergence for Information Technology
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• v.10 no.6
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• pp.41-48
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• 2020

The sensor nodes in underwater IoT networks have practical limitations in power supply. Thus, the reduction of power consumption is one of the most important issues in underwater environments. In this regard, AMC(Adaptive Modulation and Coding) techniques are used by using the relation between SNR and BER. However, according to our hands-on experience, we observed that the relation between SNR and BER is not that tight in underwater environments. Therefore, we propose a deep learning based MLP classification model to reflect multiple underwater channel parameters at the same time. It correctly predicts BER with a high accuracy of 85.2%. The proposed model can choose the best parameters to have the highest throughput. Simulation results show that the throughput can be enhanced by 4.4 times higher than the conventionally measured results.

• Journal of Korea Water Resources Association
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• v.51 no.10
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• pp.839-852
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• 2018

The purpose of this study is to predict monthly agricultural reservoir storage by developing weather data-based Multiple Linear Regression Model (MLRM) with precipitation, maximum temperature, minimum temperature, average temperature, and average wind speed. Using Naïve-Bayes classification, total 1,559 nationwide reservoirs were classified into 30 clusters based on geomorphological specification (effective storage volume, irrigation area, watershed area, latitude, longitude and frequency of drought). For each cluster, the monthly MLRM was derived using 13 years (2002~2014) meteorological data by KMA (Korea Meteorological Administration) and reservoir storage rate data by KRC (Korea Rural Community). The MLRM for reservoir storage rate showed the determination coefficient ($R^2$) of 0.76, Nash-Sutcliffe efficiency (NSE) of 0.73, and root mean square error (RMSE) of 8.33% respectively. The MLRM was evaluated for 2 years (2015~2016) using 3 months weather forecast data of GloSea5 (GS5) by KMA. The Reservoir Drought Index (RDI) that was represented by present and normal year reservoir storage rate showed that the ROC (Receiver Operating Characteristics) average hit rate was 0.80 using observed data and 0.73 using GS5 data in the MLRM. Using the results of this study, future reservoir storage rates can be predicted and used as decision-making data on stable future agricultural water supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• Journal of Convergence Society for SMB
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• v.6 no.4
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• pp.93-98
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• 2016

Recently, the project related to the smart grid are being actively studied around the developed world. In particular, the long-term stabilization measures distributed power supply problem has been highlighted. In this paper, we propose a three-dimensional numerical weather prediction models to compare the error rate information which combined with the physical models and statistical models to predict the output of distributed power. Proposed model can predict the system for a stable power grid-can improve the prediction information of the distributed power. In performance evaluation, proposed model was a generation forecasting accuracy improved by 4.6%, temperature compensated prediction accuracy was improved by 3.5%. Finally, the solar radiation correction accuracy is improved by 1.1%.