• 한국재료학회:학술대회논문집
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• 한국재료학회 1996년도 재료학회 춘계학술발표회
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• pp.64-64
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• 1996

• 전자공학회논문지A
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• 제33A권10호
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• 대한전자공학회논문지SD
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• 제42권8호
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• pp.53-60
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• 2005

최근 낮은 기가비트급 광통신 집적회로의 구현에 sub-micron CMOS 공정이 적용되고 있다. 본 논문에서는 표준 0.35mm CMOS 공정을 이용하여 4채널 3.125Gb/s 차동 전치증폭기 어레이를 구현하였다. 설계한 각 채널의 전치증폭기는 차동구조로 regulated cascode (RGC) 설계 기법을 이용하였고, 액티브 인덕터를 이용한 인덕티브 피킹 기술을 이용하여 대역폭 확장을 하였다 Post-layout 시뮬레이션 결과, 각 채널 당 59.3dBW의 트랜스임피던스 이득, 0.5pF 기생 포토다이오드 캐패시턴스에 대해 2.450Hz의 -3dB 대역폭, 그리고 18.4pA/sqrt(Hz)의 평균 노이즈 전류 스펙트럼 밀도를 보였다. 전치증폭기 어레이의 공급전원은 단일전압 3.3V 이고, 전력소모는 92mw이다. 이는 4채널 RGC 전치증폭기 어레이가 저전력, 초고속 광인터컨넥트 분야에 적합함을 보여준다.

• 한국정보통신학회논문지
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• 제13권11호
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• pp.2378-2384
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• 2009

본 논문에서는 $1{\mu}s$이하의 아주 짧은 위상고정시간을 가지는 새로운 방식의 위상고정루프(Phase Locked Loop, PLL)를 제안하였다. 지연고정루프(Delay Locked Loop, DLL)를 사용하여 입력 주파수를 체배 시켜 위상 고정 루프가 보다 더 높은 루프 대역폭을 가지도록 하여 위상고정이 짧은 시간에 일어나도록 설계하였다. 제안한 위상고정루프는 기존의 위상고정루프와 지연고정루프, 주파수 체배기로 구성되었으며 전원전압은 1.8V를 사용했다. $0.18{\mu}m$ CMOS 공정으로 Hspice를 이용해서 시뮬레이션 했으며 채널 변환 시 위상고정 시간은 $0.9{\mu}s$이다. 입력과 출력 주파수는 각각 162.5MHz, 2.6GHz이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.7-7
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• 2009

In this paper, we investigated the dependence of HCI (Hot Carrier Immunity) degradation and device performance on channel orientation in sub-micron PMOSFET. Although device performance ($I_{D.sat}$ vs. $I_{Off}$) was improved as the transistor angle increased HC immunity was degraded. Therefore, consideration of reliability characteristics as well as dc device performance is highly necessary in channel stress engineering of next generation CMOSFETs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1003-1006
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• 2003

본 논문에서는 sub-micron 소자에서 SCE(Short Channel Effect) 억제를 위한 Halo 와 SSR(Super Steep Retrograde Well) 적용에 따른 analog 특성의 열화를 석하고 이를 개선하기 위해 Twist 이온주입과 In, Sb Halo 를 채택하였다. Analog 특성은 CMOS 의 amplifier 과 Comparator 로의 사용을 고려해 Drain Rout과 Early voltage를 이용해 나타내었으며 Digital 성능을 함께 고려하였다. 실험결과 NMOS 의 경우 45 twist Halo 조건에서, PMOS의 경우 As보다 Sb를 Halo 로 적용하는 경우 더 우수한 analog 특성을 나타내었다.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.