• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1476-1480
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• 1987

This paper proposes a design method for SCLA(sequential CMOS Domino Logic Array) using 1-level CMOS Domino Logic and Stable Shift Register Latch. Also an algorithm to generate a test sequence and a test procedure for the SCLA are presented. The SCLA has advantages of low power consumption, high density and high speed, and performs hazard-and race-free logic operation, because of using SSRL(Stable Shift Register Latch). By using the proposed test method, all of stuck-at, cross-point, stuck-on and stuck-open faults in SCLA are detected by short test sequence.

• 유체기계공업학회:학술대회논문집
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• 2005.12a
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• pp.607-612
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• 2005

Check valves playa vital role in the operation and protection of nuclear power plants. Check valves failure in nuclear power plants often lead to a plant transient or trip. An overview of the failure history of check valves needs to identify key area where resources can be best applied to further improve their reliability, and provide cost effective means for failure reduction. The analysis of historical failure data gives information on the populations of various types of check valves, the systems they are installed in, failure modes, effects, methods of detection, and the mechanisms of the failures. The results presented are based on information derived from operating records, nuclear industry reports, manufacturer supplied information. A majority of check valve failures are caused by improper application. Failure modes are identified for swing and lift check valves. Failures involving improper seating and valve disc stuck comprised the largest percentage of failures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1118-1127
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• 1990

In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1551-1555
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• 1987

This paper proposes a new test generation algorithm to detect stuck-open faults regardless of tine-skews in CMOS circuits. For testing for stuck-open faults regardless of time-skews, in this method, Hamming distance between the initialization pattern and the test pattern is made 1 by considering the responses of the internal gates. Therefore, procedure of the algorithm is simpler than that of the conventional methods because the line justification is unnecessary. Also, this method needs no extra hardware for testability and can be applied to random CMOS circuits in addition to two-level NAND - NAND CMOS circuits.

• Nuclear Engineering and Technology
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• v.36 no.6
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• pp.497-511
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• 2004

A PSV (pressurizer safety valve) popping test carried out in the early phases of a refueling outage may trigger a test-induced LOCA(loss of coolant accident) if a PSV fails to fully close and is stuck in a partially open position. According to a KSNP (Korea standard nuclear power plant) low power and shutdown PSA (probabilistic safety assessment), the failure of a high pressure safety injection (HPSI) accompanied by the failure of a PSV to fully close was identified as a dominant accident sequence with a significant impact on low power and shutdown risks (LPSR). In this study, we aim to investigate and verify a new means for mitigating this type of accident using a thermal-hydraulic analysis. In particular, we explore the applicability of an aggressive cool-down combined with operator actions. The results of the various sensitivity studies performed there will help reduce LPSR and improve Refueling outage safety.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1972-1975
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• 2002

A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.71-79
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• 2000

The original March algorithms cannot detect CMOS ADOFs(Address Decoder Open Faults) which requires separate deterministic test patterns. Modified March algorithm using DOF(Degree of Freedom) was suggested to detect these faults in addition to conventional stuck faults. This paper augments the modified march test to further capture NPSFs(Neighborhood Pattern Sensitive Faults). Complete CA(Cellular Automata) is used for address generation and Rl-LFSRs(Randomly Inversed LFSRs) for data generation. A new modified March algorithm can detect SAF, CF, TF, CMOS ADOFs, and part of NPSFs. Time complexity of this algorithm is still O(n).

• Nuclear Engineering and Technology
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• v.48 no.4
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• pp.870-880
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• 2016

A steam generator tube rupture (SGTR) event with a stuck-open safety relief valve constitutes one of the most serious accident sequences in pressurized water reactors (PWRs) because it may create an open path for radioactive aerosol release into the environment. The release may be mitigated by the deposition of fission product particles on a steam generator's (SG's) dry tubes and structures or by scrubbing in the secondary coolant. However, the absence of empirical data, the complexity of the geometry, and the controlling processes have, until recently, made any quantification of retention difficult to justify. As a result, past risk assessment studies typically took little or no credit for aerosol retention in SGTR sequences. To provide these missing data, the Paul Scherrer Institute (PSI) initiated the Aerosol Trapping In Steam GeneraTor (ARTIST) Project, which aimed to thoroughly investigate various aspects of aerosol removal in the secondary side of a breached steam generator. Between 2003 and 2011, the PSI has led the ARTIST Project, which involved intense collaboration between nearly 20 international partners. This summary paper presents key findings of experimental and analytical work conducted at the PSI within the ARTIST program.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1507-1511
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• 1987

This paper proposes a NAND-NAND logic sequential Programmable Logic Array (PLA) using CMOS technology, and test generation methods about stuck-open faults. By using LSSD (Level Sensitive Scan Design) method instead of Flip-Flops in Sequential PLA, the complex test problems of sequential logic are simplified. After generating the test sets using connection graph, regular test sequences and all transistor faults detection method in PLA are proposed. Finally, by programming these algorithms in PASCAL at VAX 8700 and adopting these to pratical CMOS Sequential PLA circuits, we proved the effectiveness of this design.