• Journal of Power Electronics
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• v.19 no.3
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• pp.645-654
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• 2019

In this paper, a new high step up DC/DC converter with a modified super-lift technique is presented. The coupled inductor technique is combined with the super-lift technique to provide a tenfold or more voltage gain with a proper duty cycle and a low turn ratio. Due to a high conversion ratio, the voltage stress on the semiconductor devices is reduced. As a result, low voltage ultra-fast recovery diodes and low on resistance MOSFET can be used, which improves the reverse recovery problems and conduction losses. This converter employs a passive clamp circuit to recycle the energy stored in the leakage inductance. The proposed convertor features a high conversion ratio with a low turn ratio, low voltage stress, low reverse recovery losses, omission of the inrush currents of the switch capacitor loops, high efficiency, small volume and reduced cost. This converter is suitable for renewable energy applications. The operational principle and a steady-state analysis of the proposed converter are presented in details. A 200W, 30V input, 380V output laboratory prototype circuit is implemented to confirm the theoretical analysis.

• Proceedings of the Korea Water Resources Association Conference
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• 2006.05a
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• pp.1631-1635
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• 2006

본 연구에서는 레이놀즈응력모형(RSM: Reynolds Stress Model)을 이용하여 사다리꼴 개수로 흐름을 수치모의 하였다. 측벽 경사에 따른 사다리꼴 개수로 흐름을 수치모의 하였으며 계산된 평균유속 분포는 기존의 실험 결과와 비교하였다. 그 결과 개발된 레이놀즈응력이 사다리꼴 개수로 흐름을 비교적 잘 예측하는 것으로 나타났다. 또한 사다리꼴 수로에서는 직사각형 개수로 흐름과 달리 velocity dip 현상이 발생하지 않는 것으로 나타났다. 특히 측벽 경사가 32..인 사다리꼴 수로에서의 평균유속 및 바닥 전단응력 분포는 측벽 경사가 큰 경우와 다른 형태의 평균유속 및 전단응력 분포가 형성되는 것으로 나타났다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.8
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• pp.1547-1554
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• 2011

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

• Journal of Ocean Engineering and Technology
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• v.12 no.3 s.29
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• pp.75-85
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• 1998

A finite difference model for predicting time-dependent, wave-induced nearshore current is studied. The model includes wave refraction, wave-current interaction, bottom friction and wind effect. This model iteratively solved the linear the linear set of conservation of both mass and momentum, which were time averaged (over one wave period) and depth integrated, for mean velocities and free surface displacement. Numerical simulations of nearshore current under oblique wave attack, and for wave and wind induced current on a longshore periodic beach are carried out. Longshore velocities tend to zero in some distances outside the breaker line. And the peak velocity is shifted shoreward at the breaker line. The results represent the general characteristics of the nearshore current induced by wave.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.64-70
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• 1994

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.10a
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• pp.36-39
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• 2000

This paper presents the technology of condition diagnosis & life estimation on insulation system of the traction motor. In the non-destructive methods for diagnosis of coil insulation state, residual dielectric strength is estimated by the D-map which consist of the partial discharge quantity Q and average degradation degree $\Delta$. In the operating history of machine, the N-Y life estimation method is based on the stop-starting numbers and operating times with considering each degradation factor by the thermal, electrical and heat-cycle stress. With the on-line conditioning monitoring on the currents of traction motors, detecting the abnormal operating state due to bearing faults, stator or armature faults, eccentricity related faults and broken rotor bars can be performed.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.68-70
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• 2006

A new low-cost energy-recovery circuit (ERC) for a plasma display panel (PDP) is proposed. It has two auxiliary switches clamped on a half sustain voltage, and inductor currents are built up before the PDP is charged and -discharged. Therefore, it features a low cost, fully charged/discharged PDP, zero voltage switching (ZVS), low electromagnetic interference (EMI), low current stress, no severe voltage notch, and high energy-recovery capability.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.78-80
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• 2006

A new low-cost asymmetric current-fed energy-recovery circuit (ERC) for a plasma display panel (PDP) is proposed. LC resonant circuit biased by $V_s/2$ and composed of single switch is used as ERC on both sides of the PDP, slow discharging and fast charging times can be employed, and inductor currents are built up before the PDP is charged and discharged. Therefore, it features a low cost, fully charged/discharged PDP, zero voltage switching (ZVS), low electromagnetic interference (EMI), low current stress, no severe voltage notch, and high energy-recovery capability.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.12
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• pp.601-608
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• 2001

The ever increasing density of adjustable speed drives(ASD) device with non-linear operating characteristics has been to put tremendous harmonic stress on end user's electrical application. All ASD controllers which employ solid state power devices cause harmonic currents in the source side line. This paper describes harmonic problems for use of ASD. In order to investigate the effect of harmonics caused by using of nonlinear load at the low voltage system, we fixed up simple load model and measured the voltage and current waveforms. Measurement results show that additional operation of linear load at the parallel bus with nonlinear load such as ASD is helpful to the reduction of harmonic influence.

• 한국해양학회지
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• v.18 no.1
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• pp.10-20
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• 1983

A thee-dimensional hydrodynamic numerical model of Kyonggi Bay is described. Experiments have been performed with the model to determine the response of the bay to stationary wind stress fields suddenly imposed on the bay for wind directions of uniform NW, W and stresses of 10 dyne/$\textrm{cm}^2$ respectively. Features of the wond onduced three-dimensional current structure determined from the computation have been examined and discussed. M$\_$2/ tidal currents have also been which are dominant in the region. Some of preliminary results are preaented and discussed.