• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.344.1-344.1
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• 2016

Recently, graphene has shown great characteristic of electrical conductivity, strength, and elasticity. However, due to edge unstable and metallic properties, it is difficult to use as a semiconductor devices. The solution of such problems has been sought a way to use the boron nitride in a stacked layer structure. By graphene and boron nitride stacked layer structure on silicon substrate, the electron mobility is improved and deteriorated results in semiconductor properties. In this study, to make layered structure, we developed direct synthesis method for graphene on boron nitride. By using Raman technique, the directly stacked layer structure is in good agreement with measurements on each of the attributes.

• Journal of Sensor Science and Technology
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• v.22 no.4
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• pp.256-261
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• 2013

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• Journal of the Korea Society of Computer and Information
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• v.27 no.1
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• pp.33-41
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• 2022

This paper describes a planar microstrip patch antenna designed on dielectric substrate. Two types of planar microstrip patch antennas are studied for the 5G wireless applications, one type is conventional microstrip structure, the other type is stacked microstrip structure fed by coaxial probe. Using electromagnetically coupling method, stacked microstrip patch antenna employing a multi-layer substrate structure was designed. The results indicate that the proposed stacked microstrip patch antenna performs well at 5G wireless service bandwith a broadband from 3.42GHz to 3.70GHz. The impedance bandwidth(VSWR≤2) is 360MHz(10.28%) from 3.42GHz to 3.78GHz. In this paper, through the designing of a stacked microstrip patch antenna, we have presented the availability for 5G wireless repeater system.

• Current Optics and Photonics
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• v.7 no.2
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• pp.200-206
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• 2023

Near-infrared (NIR) sensing technology using CMOS image sensors is used in many applications, including automobiles, biological inspection, surveillance, and mobile devices. An intuitive way to improve NIR sensitivity is to thicken the light absorption layer (silicon). However, thickened silicon lacks NIR sensitivity and has other disadvantages, such as diminished optical performance (e.g. crosstalk) and difficulty in processing. In this paper, a pixel structure for NIR sensing using a stacked CMOS image sensor is introduced. There are two photodetection layers, a conventional layer and a bottom photodiode, in the stacked CMOS image sensor. The bottom photodiode is used as the NIR absorption layer. Therefore, the suggested pixel structure does not change the thickness of the conventional photodiode. To verify the suggested pixel structure, sensitivity was simulated using an optical simulator. As a result, the sensitivity was improved by a maximum of 130% and 160% at wavelengths of 850 nm and 940 nm, respectively, with a pixel size of 1.2 ㎛. Therefore, the proposed pixel structure is useful for NIR sensing without thickening the silicon.

• Journal of IKEEE
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• v.22 no.4
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• pp.1088-1092
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• 2018

In this paper, we propose a dual-mode frequency tripler using push-push and stacked FET structures. The proposed circuit can operate either in frequency multiplier mode or in amplifier mode. In the frequency multiplier mode, push-push frequency multiplication is achieved by allowing input signals with particular phase shifts. In the amplifier mode, the device operates as a distributed amplifier to obtain high gain. Also both modes were designed using stacked FET structure. The designed circuit showed frequency tripled output power of 9.7 dBm at 2.4 GHz with the input at 800 MHz. On the other hand, in the amplifier mode, the device showed 8.9 dB of gain to generate 19.5 dBm at 800 MHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1001-1006
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• 2005

A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.10
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• pp.3211-3229
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• 2022

To solve the problems existing in the process of Weibo disaster rumor recognition, such as lack of corpus, poor text standardization, difficult to learn semantic information, and simple semantic features of disaster rumor text, this paper takes Sina Weibo as the data source, constructs a dataset for Weibo disaster rumor recognition, and proposes a deep learning model BERT_AT_Stacked LSTM for Weibo disaster rumor recognition. First, add adversarial disturbance to the embedding vector of each word to generate adversarial samples to enhance the features of rumor text, and carry out adversarial training to solve the problem that the text features of disaster rumors are relatively single. Second, the BERT part obtains the word-level semantic information of each Weibo text and generates a hidden vector containing sentence-level feature information. Finally, the hidden complex semantic information of poorly-regulated Weibo texts is learned using a Stacked Long Short-Term Memory (Stacked LSTM) structure. The experimental results show that, compared with other comparative models, the model in this paper has more advantages in recognizing disaster rumors on Weibo, with an F1_Socre of 97.48%, and has been tested on an open general domain dataset, with an F1_Score of 94.59%, indicating that the model has better generalization.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.457-461
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• 2009

In this paper, barrier height between Ni-silicide and source/drain is reduced utilizing Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. It is shown that the barrier height is decreased by Pd incorporation and is dependent on the Pd thickness. Therefore, Ni-silicide using the Pd stacked structure is promising for high performance nano-cale PMOSFET.

• ETRI Journal
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• v.20 no.2
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• pp.231-240
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• 1998

We report, for the first time, the fabrication of vertically stacked InGaAs/GaAs quantum wires (QWRs) on V-grooved substrates by chemical beam epitaxy (CBE). To fabricate the vertically stacked QWRs structure, we have grown the GaAs resharpening barrier layers on V-grooves with (100)-(322) facet configuration instead of (100)-(111) base at 450 $^{\circ}C$. Under the conditions of low growth temperature, the growth rate of GaAs on the (322) sidewall is higher than that at the (100) bottom. Transmission electron microscopy verifies that the vertically stacked InGaAs QWRs were formed in sizes of about $200{\AA} {\times} 500{\sim}600 {\AA}$. Three distinct photoluminescence peaks related with side-quantum wells (QWLs), top-QWLs and QWRs were observed even at 200 K due to sufficient carrier and optical confinement. These results strongly suggest the existence of the quantized state in the vertically stacked InGaAs/GaAs QWRs grown by CBE.