• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.45-53
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• 2013

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.6
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• pp.497-504
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• 2014

The digital signage display is actively researched as the next generation of large FPD. To commercialize those digital signage display, the manufacturing cost must be downed with printing method instead of conventional photolithography. Here, we demonstrate a reverse offset printed TFT electrodes for the digital signage display. For the fabricated source/drain and gate electrode, we used Ag ink, silicone blanket, Clich$\acute{e}$ and reverse offset printer. We printed uniform TFT electrode patterns with narrow line width(10 ${\mu}m$ range) and thin thickness(nm range). In the end the printing source/drain and gate electrode are successfully achieved by optimization of experimental conditions such as Clich$\acute{e}$ surface treatment, ink coating process, delay time, off/set process and curing temperature. Also, we checked that the printing align accuracy was within 5 ${\mu}m$.

• Proceedings of the Korean Geotechical Society Conference
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• 1999.10a
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• pp.87-94
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• 1999

Sand drain as a vertical drainage is widely used in soft ground improvement. Recently, sand, the principal source of sand drain, is running out. A laboratory model test was carried out to utilize gravel as a substitute for sand. Though which the characteristics of gravel are compared to those of sand for engineering purpose. Two cylindrical containers for the model test were filled with marine clayey soil from the west coast of Korea with a column in the center, one with sand, the other with gravel. Vibrating wire type piezometers were installed at the distance of 1.0D, 1.5D and 2.0D from the center of the column. D is the diameter of the column. The transient process of pore water pressure with loading and the characteristics of consolidation were studied with the data gained from the measuring instrument place on the surface of the container. The parameter study was performed for the marine clayey soil before and after the test in order to check the effectiveness of the improvement. The clogging effect was checked at various depth in gravel column after the test. According to the test, the settlement was found to be smaller in gravel drain than in sand drain. The increase in bearing capacity by gravel pile explains the result. The clogging effect was not found in gravel column. As a result, it is assumed that gravel is relatively acceptable as a drainage material.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.51-58
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• 1995

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si cosumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the cosumed Si source during Ti silicidation. This method was applied to the actual fabrication of PMOSFET through SES (selectricely etched Si) techology.

• Journal of Information Display
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• v.6 no.4
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• pp.6-10
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• 2005

The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.7-13
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• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

• Journal of the Korean Geosynthetics Society
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• v.4 no.1
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• pp.27-36
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• 2005

Discharge capacity of the fiber mat and the fiber drain made with natural fibers abstracted from plant source was evaluated by permeability test for fiber mat and Delft type test and composite discharge capacity test using disturbed clayey soils for fiber drain. The permeability test results for environmentally friendly coconut fiber mat prove that fiber mat has outstanding permeability in substituting permeable sand. However, discharge capacity of fiber drain evaluated by conventional Delft type discharge capacity test was relatively lower than that of plastic drain board. Nevertheless, settlement and pore pressure dissipation behaviors of fiber drain and plastic drain board installed clay soil during the composite discharge capacity test were almost similar to that of plastic drain board. It is found that the natural fiber drain satisfies requiring minimum discharge capacity in substituting the conventional plastic drain board.

• Journal of Sensor Science and Technology
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• v.26 no.2
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• pp.79-84
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• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.197-202
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• 2008

In this paper, we proposed an analytical model for TFT which has series of the polycrystalline structures. An average speed is defined as carrier speed by the electric field. The effective square is suggested as the area of grain without depletion for the changed grain size. First, physical parameters such as grain size, channel lenght and trap density, have been changed to prove the validity of the average speed model and the value of the effective square has been estimated through drain-source current.