• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.50-57
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• 2011

Conventional bus system architectures are composed of several components such as master, arbiter, decoder and slave modules. The arbiter plays a role in bus arbitration according to the selected arbitration method, since several masters cannot use the bus concurrently. Typical priority strategies used in high performance arbiters include static priority, round robin, TDMA and lottery. Typical arbitration algorithms always consider the bus priority primarily, while the bus utilization is always ignored. In this paper, we propose an arbitration method using bus utilization for the operating block of each master. We verify the performance compared with the other arbitration methods through the TLM(Transaction Level Model). Based on the performance verification, the conventional fixed priority and round-robin arbitration methods cannot set the bus utilization. Whereas, in the case of the conventional TDMA and lottery arbitration methods, more than 100,000 cycles of bus utilization can be set by the user, exhibiting differences of actual bus utilization up to 50% and 70%, respectively. On the other hand, we confirm that for the proposed arbitration method, the matched bus utilization set by the user was above 99% using approximately 1,000 cycles.

• Journal of IKEEE
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• v.28 no.1
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• pp.116-122
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• 2024

AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.390-398
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• 2004

This paper describes a study on the automatic generation system of the interface for communication among AMBA bus and IPs with different protocols. Employing an extended STG, the proposed system generates the interface modules required for the communication among IPs with different protocols. For an example system, the interface module for communication between AMBA AHB bus and a video decoder has been generated and verified in its functionality. The area and latency have been compared with the manually designed interface. For burst-mode communication, the generated interface module shows the comparable performance with the manually designed module. For single-mode communication, the generated interface module shows a slightly worse performance than the manually designed module. However, the increased area is negligible considering the size of the IP.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1733-1736
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• 2005

본 논문에서는 기존의 설계 방법의 문제점을 해결하기 위한 설계 방법인 플랫폼 기반 설계에서 사용할 수 있는 DSP 기반 플랫폼을 구현하였다. 구현된 DSP 기반 플랫폼을 AMBA AHB 버스를 바탕으로한 듀얼프로세서 플랫폼과 crossbar switch 구조의 버스 구조를 가지고 4개의 프로세서를 연결한 멀티프로세서 플랫폼으로 확장하여 검증함으로서 이질적인 환경에서 동작함을 나타내었다. 멀티프로세서 플랫폼에서는 DVB-T baseband 수신기를 HW/SW 분할 구현하고 성능 평가를 수행하였다. DSP 기반 플랫폼은 유연성, 확장성, 고속의 연산의 특징을 가진다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.46-51
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• 2010

We propose the novel Hybrid bus arbitration policy that prevents a priority monopolization presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitrations. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and area overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others and effectively controls the bus utilization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.63-65
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• 2021

This paper describes an integrated H/W-S/W implementation of elliptic curve digital signature algorithm (EC-DSA) using a security system-on-chip (SoC). The security SoC uses the Cortex-A53 APU as CPU, and the hardware IPs of high-performance elliptic curve cryptography (HP-ECC) core and SHA3 (secure hash algorithm 3) hash function core are interfaced via AXI4-Lite bus protocol. The signature generation and verification processes of EC-DSA were verified by the implementation of the security SoC on a Zynq UltraScale+ MPSoC device.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1375-1378
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• 2003

다중 프로세서 내장 SoC의 동작 검증에는 많은 연산과 시간을 필요로 한다. 본 논문에서는 듀얼 프로세서 내장 SoC AISC의 검증을 위해 가상 명령어 세트를 기반으로 한 프로그램 소프트웨어 모델(PSM)과 버스 트랜잭션을 발생시키는 프로세서 마크로 엔진 모델(PEM)을 사용한 검증 방법을 제시한다. 제시된 방법은 추상화된 가상 마크로 엔진 명령 세트를 사용함으로써, 적은 컴퓨팅 리소스로 다중프로세서 내장 SoC의 검증을 보다 빠르게 수행할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.12
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• pp.1170-1178
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• 2013

Thanks to various benefits, low-cost real-time communication networks so called fieldbus have been widely used in many industrial applications including military systems, such as aircrafts, submarines, and robots. This paper presents a reliability analysis of dual-channel CAN(Controller Area Network) fieldbus which is used for controlling various equipment of submarine combat system. A submarine combat system playing a critical role to the success of missions and survivability consists of various devices including sensors/actuators and computers. Since a communication network for submarine combat system must satisfy an extremely high level of reliability, a dual channel technique is commonly adopted. In this paper, a Petri Net based reliability model for dual-channel CAN is discussed. A reliability model called generalized stochastic Petri Nets (GSPN) is built by utilizing the information on physical faults with CAN. The effectiveness of the proposed model is analyzed in terms of unreliability with respect to failure rate and repair rate.