• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.7
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• pp.657-663
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• 2009

A fully integrated single ended IR-UWB receiver is implemented using 0.18 ${\mu}m$ CMOS technology. The UWB receiver adopts the non-coherent architecture, which simplifies the RF architecture and reduces power consumption. The receiver consists of single-ended 2-stage LNAs, S2D, envelope detector, VGA, and comparator. The measured results show that sensitivity is -80.8 dBm at 1 Mbps and BER of $10^{-3}$. The receiver uses no external balun and the chip size is only $1.8{\times}0.9$ mm. The consumed current is very low with 13 mA at 1.8 V supply and the energy per bit performance is 23.4 nJ/bit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.185-185
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• 2008

This paper describes the broadband SDC (Single-ended to Differential Converter) for Digital Video Broadcasting-Satellite $2^{nd}$ edition (DVB-S2) receiver tuner IC. It is fabricated by using $0.18{\mu}m$ CMOS process. In order to obtain high linearity and low phase mismatch, the broadband SDC (Single-ended to Differential Converter) is designed with current mirror structure and cross-coupled capacitor and current source binding differential structure at VDD. The simulation result of SDC shows IIP3 of 11.9 dBm and IIP2 of 38 dBm. It consumes 5mA current with 2.7V supply voltage.

• Journal of the Optical Society of Korea
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• v.20 no.2
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• pp.223-227
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• 2016

The impact of optical receiver configuration on in-band crosstalk-induced penalty has been investigated in both theoretical and experimental analyses, for differential phase-shift keying (DPSK) and differential quadrature phase-shift keying (DQPSK) signals. Previously it has been shown that DPSK signals are ~6 dB more tolerant to in-band crosstalk than on-off keying (OOK) signals. However, we find that the tolerance difference between the two signals is reduced to ~3 dB when the decision threshold of the receiver is optimized to minimize the bit-error rate for each signal. Then we derive simple equations for the in-band crosstalk-induced penalty in DPSK and DQPSK signals with two different optical receiver configurations: balanced and single-ended direct-detection receivers. We confirm that the penalties obtained from our simple equations agree well with the measured results.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of IKEEE
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• v.23 no.3
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• pp.1046-1053
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• 2019

In a multi-channel single-ended system, the far-end crosstalk (FEXT) due to mutual inductance and mutual capacitance between two adjacent channels critically limit the bandwidth. FEXT causes crosstalk-induced jitter (CIJ) and crosstalk-induced glitch (CIG) which leads to timing margin and voltage margin degradations, respectively. Therefore, FEXT must be compensated in order to increase eye opening and achieve high data-rate. It can be compensated in transmitter by controlling the timing of the data or reshaping the waveform of the signal. Also, FEXT can be compensated in receiver by generating mimicked FEXT using high-pass filter. In this paper, recent techniques to compensate FEXT are investigated, with discussions of their pros and cons.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.685-694
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• 2018

In this paper, we designed and fabricated the frequency mixer, which is the core parts of high frequency head in Ku-band tracking radar. To overcome the problem of single-ended and single-balanced resistive structure, we designed the fine-line structure with balanced mixer, to generate IF signal without distortion in L-band, after receiving the RF signal of the Ku-band. The prototype mixer showed a Noise Figure Max of 6.823dB, Gain of 4.1598~4.676dB and Band Pass of 61MHz in 5 Ku-band samples frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.817-824
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• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Smart Media Journal
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• v.4 no.2
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• pp.55-61
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• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.