• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of Korea Multimedia Society
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• v.16 no.1
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• pp.50-55
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• 2013

This article presents a simple and reasonable in-service, real-time, and continuous single-ended objective video quality assessment model for DTV broadcasting using a multiburst signal at the bottom of the transient effect area, similar to Vertical Interval Test Signals. The issue of in-service video-quality monitoring in DTV broadcasting is addressed, and an effective method of quality monitoring is presented. The proposed method is also implemented and tested in a range of situations using a simulated HDTV broadcasting network.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1522-1530
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• 2008

This paper presents a discrete wavelet analysis based algorithm to address the fault impedance calculation under transient state in radial power distribution networks. The fault impedances have been derived under different fault conditions. Furthermore, a recursive fault distance estimation method is proposed utilizing the measured fault impedance and power line parameters. The proposed scheme can resolve the errors caused by the non-homogeneous power lines, the presence of lateral loads since, the fault impedance will always be updated with the recursive form. For the verification of the proposed scheme, a filed test has been peformed with varying fault resistances in the 22.9(kV) radial system. Power meters and fault locators were installed at the substation. It was figured out that the performance of the discrete wavelet and the recursive scheme are very good even for high fault resistance condition.

• Journal of Power Electronics
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• v.16 no.2
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• pp.447-454
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• 2016

A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.11
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• pp.568-574
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• 2001

This paper describes a current fed high frequency resonant inverter can be used as the power supply for wax-sealing. This circuit configuration is composed of conventional two unit inverter of single ended current find type in parallel. The proposed inverter can realize ZVS operation by using resonant capacitor to ZVS capacitor and has merits not only reduction of switch current distribution but also extension of load range in comparison with the conventional single-ended current fed high frequency resonant inverter. This analysis of proposed circuit uses normalized parameter and characteristic estimation which is needed in each step before design is generally described according to normalized frequency($\mu$), normalized resistance(λ) and parameters. On the basis of characteristic values, a method of the circuit design is presented. Also, the theoretical analysis is proved through experiment and this proposed circuit shows that it can be practically used as the power supply system for wax-sealing and DC-DC converter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1632-1638
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• 2008

This paper presents a method to design CPW (coplanar waveguide) balanced amplifiers using the existing CPW wilkinson balun. In order to realize the required power dividing/combining structure for balanced amplifiers, the CPP wilkinson balun is adopted. The proposed CPW balanced amplifier has much better matching performances than the CPW single-ended amplifier. The measured frequency bands, where the input and output reflection coefficients are less than -10dB, are $1.2{\sim}2.75GHz$ and $1{\sim}3.25GHz$, respectively, while the CPW single-ended amplifier has severely bad ones.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.126-133
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• 2022

This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.138-145
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• 1995

The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

• Journal of Power Electronics
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• v.9 no.4
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• pp.604-611
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• 2009

A dP/dV feedback-controlled MPPT (Maximum Power Point Tracking) method for photovoltaic power systems using II-SEPIC (Isolated Inverse-SEPIC; Single Ended Primary Inductance Converter) is presented and a current-mode dP/dV feedback-controlled MPPT method is devised to apply for the PV power converter system. A control strategy for the current-mode dP/dV feedback control system is developed in this paper and the proposed MPPT shows relatively satisfactory dynamics against rapidly changing insolation conditions. In order to verify the validity and effectiveness of the proposed method, simulations and experiments of the PV power system using II-SEPlC converter are performed. These simulation and experiment results show that the proposed method enables the PV power system to extract maximum power from the photovoltaic module against the solar insolation variation.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2000.11a
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• pp.225-230
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• 2000

This paper describes a double-ended current fed push-pull type high frequency resonant inverter used as the power supply for wax-sealing. The proposed inverter can realize ZVS operation by using resonant capacitor to ZVS capacitor and has some merits not only reduction of switch current distribution but also extension of load range compare to the conventional single-ended current fed push-pull type high frequency resonant inverter. This analysis of proposed circuit uses normalized parameter ad characteristic estimation which is needed in each step before design is generally described according to normalized frequency($\mu$), normalized resistance(λ) and parameters. It is also presented as an example of method of the circuit design based on estimation analysis values from theoretical analysis. The theoretical analysis is proved through experiment and this circuit shows that it can be used practically as the power supply system for wax-sealing and DC-DC converter.