Three-Level SEPIC with Improved Efficiency and Balanced Capacitor Voltages

Abstract

A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.

I. INTRODUCTION

Single-ended primary-inductor converters (SEPICs) have been utilized for various industry applications because of their low input current ripples [1] and output voltage up/down capabilities [2]. Unlike the buck-boost converter [3], the SEPIC features a non-inverted output voltage [4]. It uses a series capacitor to isolate the input from the output [5]. Fig. 1 shows the circuit diagram of the conventional two-level SEPIC [1], [6]. However, the main drawback of the two-level SEPIC is that the switching devices rely on the sum of the input voltage Vi and output voltage Vo [7]. When the output voltage Vo is 400 V, the power switch and output diode should be rated at 1,200 V as Vi may increase to more than 200 V. As the output voltage increases, the switch voltage stress significantly increases. This high voltage stress increases the switching losses and eventually decreases the converter efficiency and reliability.

Fig. 1.Circuit diagram of the conventional two-level SEPIC.

Three-level converters are widely adopted tools for high voltage applications [8], [9]. These converters use two series-connected capacitors to achieve total dc-link voltage. The power switches are then stressed on half of the total dc-link voltage. Three-level converters can use low voltage-rated switches and thus achieve better switching performance than two-level converters that use switches rated in terms of full blocking voltage. Moreover, the performance of three-level converters, including cost and power efficiency, can be improved in comparison with that of two-level converters. Recently, a three-level isolated SEPIC was explored in [12]. Unfortunately, the isolated-type converter requires two transformers, which increase the manufacturing cost and eventually decrease converter efficiency. However, thus far, three-level non-isolated SEPICs have not been suggested, and their performance has not been reported.

The present work proposes a three-level SEPIC whose circuit diagram is shown in Fig. 2. The three-level SEPIC can reduce switch voltage stresses by half in comparison with the two-level SEPIC. This feature allows the three-level SEPIC to have low voltage-rated switches. The three-level SEPIC improves power efficiency by reducing switching losses. The operation of the three-level SEPIC is described in Section II. The control method for regulating the output voltage and capacitor voltages is presented in Section III. The experimental results for a 500 W prototype converter are discussed in Section IV. The experimental results show that the three-level SEPIC improves power efficiency with balanced capacitor voltages in comparison with the two-level SEPIC. The concluding remarks are given in Section V.

Fig. 2.Circuit diagram of the proposed three-level SEPIC.

 

II. THREE-LEVEL SEPIC

Fig. 3 shows the circuit diagram of the three-level SEPIC with the reference directions of currents and voltages. The three-level SEPIC comprises an input inductor Li, two switches S1 and S2, two capacitors C1 and C2, an output inductor Lo, two diodes D1 and D2, and two output capacitors Co1 and Co2. Ro1 and Ro2 are the output resistors, whereas S1 and S2 are the metal-oxide-semiconductor field-effect transistors (MOSFETs). Vi is an input voltage; Vc1 and Vc2 are the voltages of C1 and C2, respectively; Vo1 and Vo2 are the voltages of Co1 and Co2, respectively; VS1 and VS2 are the voltages across S1 and S2, respectively; VD1 and VD2 are the voltages across D1 and D2, respectively; and iLi and iLo are the currents of Li and Lo, respectively. The midpoint of the output capacitors is connected to the midpoint of the series-connected switches. Co1 and Co2 serve as capacitive voltage dividers that split the output voltage Vo into two equal voltages, namely, Vo1 and Vo2 (Vo1 = Vo2 = Vo/2). Vc1 and Vc2 follow the half of the input voltage (Vc1 = Vc2 = Vi/2).

Fig. 3.Circuit diagram of the three-level SEPIC with the reference directions of currents and voltages.

Fig. 4 shows the operation waveforms of the three-level SEPIC. Vgs1 and Vgs2 are the gating signals of S1 and S2, respectively. DS1 and DS2 are the duty cycles of S1 and S2, respectively. If Vgs1 and Vgs2 are identical to a 180° phase difference with respect to one switching period Ts, then the duty cycle is considered as D. When the duty cycle D is less than 0.5, the three-level SEPIC steps down the input voltage, as shown in Fig. 4(a). When the duty cycle D is higher than 0.5, the three-level SEPIC steps up the input voltage, as shown in Fig. 4(b). Fig. 5 shows the circuit diagrams of the three-level SEPIC according to the switches’ states. Depending on the switches’ state, the three-level SEPIC has the following four operation modes.

Fig. 4.Operation waveforms of the three-level SEPIC: (a) D < 0.5 and (b) D > 0.5.

Fig. 5.Circuit diagram of the three-level SEPIC according to the switches’ state: (a) Mode I, (b) Mode II, (c) Mode III, and (d) Mode IV.

Mode I: The three-level SEPIC is in Mode I only when D > 0.5. When S1 and S2 are turned on, D1 and D2 are turned off. On the one hand, the input inductor Li stores energy from the input voltage Vi. The input inductor current iLi flows through Li, S1, and S2 at a rate of diLi/dt = Vi/Li. On the other hand, the output inductor current iLo charges the capacitors C1 and C2. The output inductor current iLo flows through C1, S1, S2, and C2 at the rate of diLo/dt = Vi/Lo.

Mode II: S1 is turned on while S2 is turned off. D1 is turned off while D2 is turned on. On the one hand, the input inductor current iLi charges the capacitors C2 and Co2. The input inductor current iLi flows through Li, S1, Co1, D2, and C2 at the rate of diLi/dt = (Vi – Vo)/2Li. On the other hand, the output inductor current iLo charges the capacitors C1 and Co2. The output inductor current iLo flows through C1, S1, C2, and D2 at the rate of diLo/dt = (Vi – Vo)/2Lo.

Mode III: S1 is turned off while S2 is turned on. D1 is turned on while D2 is turned off. On the one hand, the input inductor current iLi charges the capacitors C1 and Co1. The input inductor current iLi flows through Li, C1, D1, and Co1 at the rate of diLi/dt = (Vi – Vo)/2Li. On the other hand, the output inductor current iLo charges the capacitors C2 and Co1. The output inductor current iLo flows through D1, Co1, S2, and C2 at the rate of diLo/dt = (Vi – Vo)/2Lo.

Mode IV: The three-level SEPIC is in Mode IV only when D < 0.5. When S1 and S2 are turned off, D1 and D2 are turned on. On the one hand, the input inductor Li releases its stored energy to the output capacitors Co1 and Co2, thus discharging the capacitors C1 and C2. The input inductor current iLi flows through Li, C1, D1, Co1, Co2, D2, and C2 at the rate of diLi/dt = –Vo/Li. On the other hand, the output inductor current iLo flows through D1, Co1, Co2, and D2 at the rate of diLo/dt = –Vo/Lo.

When S1 and D2 are turned off, they are stressed on the sum of Vc1 and Vo1. When S2 and D1 are turned off, they are stressed on the sum of Vc2 and Vo2. With the assumption that Vc1 = Vc2 = Vi/2 and Vo1 = Vo2 = Vo/2, the switch voltage stress is (Vi + Vo)/2. The switch voltage stress in the three-level SEPIC is reduced by half compared with the switch voltage stress in the two-level SEPIC. This condition allows the three-level SEPIC to have low voltage-rated switches and reduce switching losses.

 

III. SIMULATION VERIFICATION

The capacitor voltages should be balanced as Vc1 = Vc2 = Vi/2 and Vo1 = Vo2 = Vo/2. In practice, capacitor voltages may be different because of mismatched capacitances and equivalent series resistance [10]. If not balanced, one capacitor voltage may be greater than the breakdown voltage of the power switch; this difference causes severe damage to the power switch [11]. Thus, capacitor voltage balance control is necessary for the three-level SEPIC.

Fig. 6 the control scheme of the three-level SEPIC. Fig. 6(a) shows the control block diagram for regulating the output voltage. To obtain the relation between the control variables and duty cycle D, Mode I and Mode II are considered for a half switching period Ts/2. When S1 and S2 are turned on during Mode I, the input inductor current iLi increases. The following voltage equation is obtained as

When S1 is turned on and S2 is turned off during Mode II, the input inductor current iLi decreases. The following voltage equation is obtained as

Depending on the duty cycle D, the average inductor voltage for Ts/2 yields the input inductor current variation △iLi as

By rearranging (3),

Here, the duty cycle D is represented as

where the nominal duty cycle Dn and controlled duty cycle Dc are represented as

To regulate the output voltage Vo to track its voltage reference Vo*, a proportional-integral (PI)-type voltage controller is used for the controlled duty cycle Dc, which is given by

The voltage error Vo,err is obtained by comparing the voltage reference Vo* with the measured output voltage Vo. kp and ki are the proportional and integral control gains of the controller, respectively.

Fig. 6.Control scheme of the three-level SEPIC: (a) control block diagram for regulating the input current and output voltage and (b) control block diagram for balancing the capacitor voltages.

Fig. 6(b) shows the control block diagram for balancing the capacitor voltages. On the one hand, the duty cycle DS1 is determined by the voltage controller. On the other hand, the duty cycle DS2 is determined by adding the duty cycles DCi and DCo to the duty cycle DS1, whose phase is shifted by 180°. The duty cycle DCi is

where kp and ki are the proportional and integral gains of the controller, respectively. VCi,err is the voltage error between Vc2 and Vc1. The duty cycle DCo is

where kp and ki are the proportional and integral gains of the controller, respectively. VCo,err is the voltage error between Vo2 and Vo1. With the suggested capacitor voltage balancing control, the capacitor voltages can be balanced. As the duty cycle DS2 is different from DS1, the load currents flowing through Ro1 and Ro2 are slightly different while the capacitor voltages are balanced.

 

IV. EXPERIMENTAL RESULTS

To evaluate the performance of the three-level SEPIC, a 500 W prototype converter is built and tested. Table I shows the electrical specification of the prototype converter. A two-level SEPIC is also designed for purposes of comparison. Table II shows the main component parameters of the two converters. On the one hand, to select the inductances of Li and Lo, the inductor ripple current is considered. The inductance is generally proportional to the voltage induced across each inductor. In addition, the duty cycle should be considered with the inductor ripple current. As the inductor ripple current increases, the minimum inductance may decrease with respect to the duty cycle for the voltage across the inductor. On the other hand, to select the capacitances of C1, C2, Co1, and Co2, the capacitors are primarily designed to reduce capacitor voltage ripples. As the capacitor voltage ripples decrease, the capacitances of the capacitor should increase. The film capacitors, as non-polarized capacitors, may be used for C1 and C2 because they follow half of the input voltage. By contrast, the electrolytic capacitors, as polarized capacitors, may be used for Co1 and Co2 because they supply electric power to the output load, thereby serving as a capacitive voltage divider that splits the output voltage into two equal voltages Vo1 and Vo1.

TABLE IELECTRICAL SPECIFICATION OF THE PROTOTYPE CONVERTER

TABLE IIMAIN COMPONENT PARAMETERS OF THE CONVERTERS

Fig. 7 shows the experimental waveforms of the two-level SEPIC for a 500 W output power. The two-level SEPIC uses 11N80C3 (Infineon) for S1, whose voltage rating is 800 V. It utilizes RHRP15120 (Fairchild) for D1, whose voltage rating is 1200 V. Fig. 7(a) shows the switch voltage VS1 and the diode voltage VD1 when the duty cycle D is 0.41 for Vi = 200 V. The balanced resistive load is used. The output voltage Vo is 140 V for Ro1 = Ro2 = 39 Ω. The switch voltage stress is theoretically calculated as 340 V. However, the peak switch voltage stress with the voltage spike is measured as 550 V. When the switch is turned off, the output diode cannot be turned off instantly. As a result of the reverse-recovery process of the diode, a large reverse-recovery current is produced. This reverse-recovery current, in turn, produces a voltage spike across the power switch. This type of switching operation is called the hard-switching operation [13]. Fig. 7(b) shows the switch voltage VS1 and diode voltage VD1 when the duty cycle D is 0.60 for Vi = 200 V. The output voltage Vo is 300 V for Ro1 = Ro2 = 180 Ω. The switch voltage stress is theoretically calculated as 500 V. However, Fig. 7(b) shows that the peak switch voltage stress with the voltage spike is measured as 700 V as a result of the hard-switching operation.

Fig. 7.Experimental waveforms of the two-level SEPIC. (a) Switch voltage VS1 and the diode voltages VD1 for D = 0.41. (b) Switch voltage VS1 and the diode voltages VD1 for D = 0.60.

Fig. 8 shows the experimental waveforms of the three-level SEPIC for a 500 W output power. The three-level SEPIC uses FQA24N50 (Fairchild) for S1 and S2, whose voltage rating is 500 V. It also employs FES8JT (Vishay) for D1 and D2, whose voltage rating is 600 V. Fig. 8(a) the switch voltages VS1 and VS2 and diode voltages VD1 and VD2 when the duty cycle D is 0.41 for Vi = 200 V. The output voltage Vo is 140 V for Ro1 = Ro2 = 39 Ω. The voltage stress of the switching devices is calculated as 170 V, which is half of the voltage stress of the switching devices in the two-level SEPIC. However, the peak switch voltage stress with the voltage spike is measured as 300 V because of the hard-switching operation. Fig. 8(b) shows the switch voltages VS1 and VS2 and diode voltages VD1 and VD2 when the duty cycle D is 0.60 for Vi = 200 V. The output voltage Vo is 300 V for Ro1 = Ro2 = 180 Ω. The voltage stress of the switching devices is calculated as 250 V. However, Fig. 8(b) shows that the peak switch voltage stress with the voltage spike is measured as 300 V because of the hard-switching operation.

Fig. 8.Experimental waveforms of the three-level SEPIC: (a) switch voltages VS1 and VS2 and the diode voltages VD1 and VD2 for D = 0.41 and (b) switch voltages VS1 and VS2 and the diode voltages VD1 and VD2 for D = 0.60.

Fig. 9 shows the experimental waveforms of the two-level SEPIC and three-level SEPIC when Vi is 200 V for D = 0.60 and for a 500 W output power. Fig. 9(a) shows the inductor current waveforms of the two-level SEPIC. The current ripple is observed as 2.0 A. The current ripple frequency is the same as the switching frequency of 50 kHz. Fig. 9(b) shows the inductor current waveforms of the three-level SEPIC. The current ripple is 1.0 A, which is two times lower than the current ripple of the two-level SEPIC. The current ripple frequency is 100 kHz, which is two times higher than the switching frequency of 50 kHz.

Fig. 9.Experimental waveforms of the two-level SEPIC and the three-level SEPIC: (a) inductor current waveforms of the two-level SEPIC and (b) inductor current waveforms of the three-level SEPIC.

Fig. 10 shows the experimental waveforms of the three-level SEPIC. Fig. 10(a) shows the capacitor voltages when the output voltage is regulated as Vo = 300 V without the capacitor voltage balance control. The three-level SEPIC is operated for Vi = 200 V, Ro1 = 86 Ω, and Ro2 = 94 Ω. As the output voltage Vo is regulated as Vo = 300 V, the output capacitor voltages Vo1 and Vo2 are unbalanced along with the capacitor voltage Vc1 and Vc2 as Vo1 = 120 V, Vo2 = 180 V, Vc1 = 160 V, and Vc2 = 40 V because the mismatched series-connected output resistances. Fig. 10(b) shows the capacitor voltages when the output voltage is regulated as Vo = 300 V with the capacitor voltage balance control. The three-level SEPIC is operated for Vi = 200 V, Ro1 = 86 Ω, and Ro2 = 94 Ω. As the output voltage Vo is regulated as Vo = 300 V, the output capacitor voltages Vo1 and Vo2 are balanced as Vo1 = 150 V and Vo2 = 150 V. In addition, the capacitor voltages Vc1 and Vc2 are balanced as Vc1 = 100 V and Vc2 = 100 V by the suggested capacitor voltage control.

Fig. 10.Experimental waveforms of the three-level SEPIC: (a) capacitor voltages when the output voltage is regulated as Vo = 300 V without the capacitor voltage balance control and (b) capacitor voltages when the output voltage is regulated as Vo = 300 V with the capacitor voltage balance control.

Fig. 11 shows the measured power efficiencies of the two-level SEPIC and three-level SEPIC. The power efficiencies are measured for different output power levels when the output voltage is controlled as Vo = 140 V and Vo = 300 V for Vi = 200 V. Fig. 11(a) demonstrates the measured power efficiencies when the output voltage is 140 V for a 500 W output power. The two-level SEPIC achieves an efficiency of 91.6%. By contrast, the three-level SEPIC achieves an efficiency of 93.4%. The three-level SEPIC improves its efficiency by 1.8% in comparison with the two-level SEPIC when the output voltage is 140 V from Vi = 200 V. Fig. 11(b) shows the measured power efficiencies when the output voltage is 300 V for a 500 W output power. The two-level SEPIC achieves an efficiency of 95.0%, whereas the three-level SEPIC achieves an efficiency of 94.0%. The three-level SEPIC improves its power efficiency by 1.0% in comparison with the two-level SEPIC when the output voltage is 300 V from Vi = 200 V for a 500 W output power. Figs. 12(a) and (b) show the photographs of the two-level and three-level SEPICs, respectively. The converters are controlled by a single-chip micro-controller, dsPIC30F2020 (Microchip). A voltage divider with an operational amplifier is designed for sensing the capacitor voltages. To generate a phase-shifted pulse width modulation (PWM) signal, a power supply PWM module in dsPIC30F2020 is utilized.

Fig. 11.Measured power efficiencies of the two-level SEPIC and three-level SEPIC: (a) power efficiencies when the output voltage is 140 V and (b) power efficiencies when the output voltage is 300 V.

Fig. 12.Photographs of the converters: (a) two-level SEPIC and (b) three-level SEPIC.

 

V. CONCLUSION

This study proposes a three-level SEPIC to overcome the drawback of the conventional two-level SEPIC. The three-level SEPIC features low switch voltage stresses as it reduces such stresses by half in comparison with the two-level SEPIC. This feature allows the three-level SEPIC to use low voltage-rated switches and reduce switching losses. The converter operation is described. The converter control for regulating the output voltage with the capacitor voltage balance control is also presented. The experimental results for a 500 W prototype converter are discussed. The experimental results indicate that the three-level SEPIC improves its power efficiency with balanced capacitor voltages in comparison with the two-level SEPIC. The three-level SEPIC improves its efficiency by 1.8% when it steps down the input voltage of 200 V to the output voltage of 140 V for a 500 W output power. The three-level SEPIC also improves its efficiency by 1.0% when it steps up the input voltage of 200 V to the output voltage of 300 V for a 500 W output power. The proposed three-level SEPIC is expected to be utilized in photovoltaic and fuel-cell power generations.