• Journal of Biosystems Engineering
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• v.41 no.4
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• pp.357-364
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• 2016

Purpose: This study was performed to define the drying characteristics of sorghum by developing thin layer drying equations and evaluating various grain drying equations. Thin layer drying equations lay the foundation characteristics to establish the thick layer drying equations, which can be adopted to determine the design conditions for an agricultural dryer. Methods: The drying rate of sorghum was measured under three levels of drying temperature ($40^{\circ}C$, $50^{\circ}C$, and $60^{\circ}C$) and relative humidity (30%, 40%, and 50%) to analyze the drying process and investigate the drying conditions. The drying experiment was performed until the weight of sorghum became constant. The experimental constants of four thin layer drying models were determined by developing a non-linear regression model along with the drying experiment results. Result: The half response time (moisture ratio = 0.5) of drying, which is an index of the drying rate, was increased as the drying temperature was high and relative humidity was low. When the drying temperature was $40^{\circ}C$ at a relative humidity (RH) of 50%, the maximum half response time of drying was 2.8 h. Contrastingly, the maximum half response time of drying was 1.2 h when the drying temperature was $60^{\circ}C$ at 30% RH. The coefficient of determination for the Lewis model, simplified diffusion model, Page model, and Thompson model was respectively 0.9976, 0.9977, 0.9340, and 0.9783. The Lewis model and the simplified diffusion model satisfied the drying conditions by showing the average coefficient of determination of the experimental constants and predicted values of the model as 0.9976 and Root Mean Square Error (RMSE) of 0.0236. Conclusion: The simplified diffusion model was the most suitable for every drying condition of drying temperature and relative humidity, and the model for the thin layer drying is expected to be useful to develop the thick layer drying model.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.270-285
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• 2005

A joint design scheme is proposed to optimize the up/down scaler and the motion vector estimation module in the transcoder system. The proposed scheme first optimizes the resolution scaler for a fixed motion vector, and then a new motion vector is estimated for the fixed scaler. These two steps are iteratively repeated until they reach a local optimum solution. In the optimization of the scaler, we derive an adaptive version of a cubic convolution interpolator to enlarge or reduce digital images by arbitrary scaling factors. The adaptation is performed at each macroblock of an image. In order to estimate the optimal motion vector, a temporary motion vector is composed from the given motion vectors. Then the motion vector is refined over a narrow search range. It is well-known that this refinement scheme provides the comparable performance compared to the full search method. Simulation results show that a jointly optimized system based on the proposed algorithms outperforms the conventional systems. We can also see that the algorithms exhibit significant improvement in the minimization of information loss compared with other techniques.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6247-6253
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• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.5
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• pp.717-722
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• 2016

In this paper, in order to support the peak current limiting function depending on the intensity of the fault current at the early stage of failure, a two magnetically coupled type superconducting fault current limiter (SFCL) is proposed, which includes high-Tc superconducting (HTSC) element 1, where the existing primary and secondary coils are connected to one iron core in parallel, and HTSC element 2, which is connected to the tertiary winding using an additional iron core. The results of the experiments in this study confirmed that the two magnetic coupling type SFCL having coil 1 and coil 2 connected in parallel using dual iron cores is capable of having only HTSC element 1 support the burden of the peak current when a failure occurs. The reason for this is that although HTSC element 1 was quenched and malfunctioned because the instantaneous factor of the initial fault current was large, the current flowing to coil 3 did not exceed the critical current, which would otherwise cause HTSC element 2 to be quenched and not function. In order to limit the peak current upon fault through the sequential HTSC elements, the design should allow it to have the same value as the low value of coil 1 while having coil 3 possess a higher self-inductance value than coil 2. In addition, a short-circuit simulation experiment was conducted to examine and validate the current limiting and recovery characteristics of the SFCL when the winding ratio between coil 1 and coil 2 was 0.25. Through the analysis of the short-circuit tests, the current limiting and recovery characteristics in the case of the additive polarity winding was confirmed to be superior to that of the subtractive polarity winding.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1021-1030
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• 2010

In the sensor network, many tiny nodes construct Ad-Hoc network using wireless interface. As this type of system consists of thousands of nodes, managing each sensor node in real world after deploying them is very difficult. In order to install the sensor network successfully, it is necessary to verify its software using a simulator beforehand. In fact Sensor network simulators require high fidelity and timing accuracy to be used as a design, implementation, and evaluation tool of wireless sensor networks. Cycle-accurate, instruction-level simulation is the known solution for those purposes. In this paper, we developed an instruction-level sensor network simulator for Telos sensor node as named TeloSlM. It consists of MSP430 and CC2420. Recently, Telos is the most popular mote because MSP430 can consume the minimum energy in recent motes and CC2420 can support Zigbee. So that TeloSlM can provide the easy way for the developers to verify software. It is cycle-accurate in instruction-level simulator that is indispensable for OS and the specific functions and can simulate scalable sensor network at the same time. In addition, TeloSlM provides the GUI Tool to show result easily.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.103-110
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• 2010

In this paper, a new mode changeable asymmetric full bridge dc/dc converter is proposed to solve the freewheeling current problem of the conventional zero voltage switching(ZVS) phase shift full bridge(PSFB) dc/dc converter of low output voltage and high output current applications. The proposed converter is operated as an asymmetric full bridge converter when the duty cycle is less than 50% and active clamp full bridge converter when the duty cycle is greater than 50%. As a result, since its freewheeling current is eliminated, the conduction loss is lower than that of the conventional ZVS PSFB dc/dc converter. Moreover, ZVS of all power switches can be ensured along a wide load ranges and output current ripple is very small. Therefore, high efficiency of the proposed converter can be achieved. Especially since its operation mode is changed to the active clamp full bridge converter during hold up time and can be operated with 50~100% duty ratio, it can produce the stable output voltage along wide input voltage range. The operational principles, theoretical analysis and design considerations are presented. To confirm the operation, validity and features of the proposed converter, experimental results from a 1.2kW($400V_{dc}/12V_{dc}$) prototype are presented.

• International Journal of Highway Engineering
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• v.12 no.4
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• pp.17-28
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• 2010

A climbing lane is installed to separate low-speed traffic from high-speed traffic if drastic traffic capacity reduction is expected due to a large number of vehicles that slow down in the upward section. Existing studies on climbing lanes have focused on the designation, location of starting and ending points, and installation method of climbing lane with regard to road design standards. However, in terms of traffic operation, it was known that the climbing lanes cause traffic congestion due to the increase of traffic volumes. In this regard, this study aims to establish traffic operational guidance as to how much effects temporary closure of climbing lanes can have on traffic improvement according to the volume-capacity ratio, grade, and composition of trucks. A test section of simulated climbing lane was selected in Nakdong JC bound for Masan(136.9K~133.3K, 3.6km, 3.7%) on Jungbunaeryuk expressway to conduct VISSIM analyses, microscopic traffic simulation based on such control variables as traffic volume(v/c), grade and the trucks ratio. As a result of the analyses, it has been found that v/c and the ratio of trucks are the key variables for efficient traffic management of climbing lanes in order to relieve traffic congestion via climbing lane. If ratio of trucks are more than 50% and when v/c would be 0.8, both climbing lane would be closed and non-operated regardless of grade and ratio of trucks when v/c is 1.0. With the increased traffic due to a five-day work week system, continued peak hours during the weekday, increased and various patterns of congestion on expressway, this study would be expected to contribute to facilitating researches on flexible operational standards for road facilities.