• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.182.1-182.1
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• 2009

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1318-1320
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• 1998

We have investigated the electrical characteristics of a MOSFET-structured silicon field emitter by employing Maxwell 2D and Silvaco simulators. The potential distribution is obtained by Maxwell 2D simulator and the field emission current is calculated by Fowler-Nordheim equations. The characteristics of MOSFET is simulated by Silvaco simulator. Simulated results are almost identical to the experimental results. Also, we have studied the emission characteristics as funtions of several geometric parameters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.711-714
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• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.393-393
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• 2011

오늘 날 태양전지 산업에서 가장 많은 생산을 하고 있는 분야는 결정질 태양전지분야이다. 현재는 이러한 시대적 요구에 따라 많은 연구가 진행되고 있는데 특히 junction을 이루는 n layer의 doping profile을 선택적으로 형성하여 개방전압 및 단락전류를 향상시키는 연구가 활발히 진행되고 있다. 본 연구는 이러한 n type layer의 doping profile을 선택적으로 형성하는 selective emitter solar cell에 관한 연구로써 SILVACO simulation을 이용하여 low Rs 영역은 고정하고 high Rs 영역의 doping depth를 가변 함으로써 high Rs 영역을 달리 형성하는 방법으로 selective emitter solar cell의 high Rs영역의 최적화에 관한 전산모사를 실시하였다. 각각의 가변조건에 따라 quantum efficiency를 통한 광학적 분석과 I-V를 통한 전기적 분석을 하여 high Rs영역을 최적화 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.26-28
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• 2001

A Trench schottky diode with guard ring is proposed to improve the forward current density and reverse breakdown voltage. The simulation results by Silvaco have shown that the reverse breakdown voltage of the proposed device was found to be 22.1V while that of conventional trench device was 17.25V. The breakdown voltage of the proposed structure was 28.1% higher than that of the conventional trench structure.