• Journal of the Korean institute of surface engineering
• /
• v.57 no.1
• /
• pp.22-30
• /
• 2024

This study reports a direct growth of carbon nanotubes (CNTs) on the surface of LiCoO₂ (LCO) powders to apply as highly efficient cathode materials in lithium-ion batteries (LIB). The CNT synthesis was performed using a thermal chemical vapor deposition apparatus with temperatures from 575 to 625 ℃. Ferritin molecules as growth catalyst of CNTs were mixed in deionized (DI) water with various concentrations from 0.05 to 1.0 mg/mL. Then, the LCO powders was dissolved in the ferritin solution at a ratio of 1g/mL. To obtain catalytic iron nanoparticles on the LCO surface, the LCO-ferritin suspension was dropped in silicon dioxide substrates and calcined under air at 550℃. Subsequently, the direct growth of CNTs on LCO powders was performed using a mixture of acetylene (10 sccm) and hydrogen (100 sccm) for 10 min. The growth behavior was characterized by scanning and transmission electron microscopy, Raman scattering spectroscopy, X-ray diffraction, and thermogravimetric analysis. The optimized condition yielding high structural quality and amount of CNTs was 600 ℃ and 0.5 mg/mL. The obtained materials will be developed as cathode materials in LIB.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.34 no.2
• /
• pp.41-47
• /
• 2024

In this study, the resistance characteristics of semi-insulating SiC single crystals grown using the PVT method were investigated, considering the purity level of SiC source powders used in PVT growth and the cooling procedure after crystal growth. Two β-SiC powders with different purities were employed, and the cooling rate after growth was adjusted to achieve various resistance values. 4-inch HPSI-SiC ingots were grown using the PVT method, utilizing SiC powders with low nitrogen concentration and relatively high nitrogen concentration. These ingots were then subjected to different cooling procedures to modify the cooling rate. Transmission/absorption spectra and crystal quality of the grown crystals were analyzed through UV/VIs/NIR spectroscopy and X-ray rocking curve analysis, respectively. Additionally, electrical properties were investigated through non-contact resistivity analysis to identify the dominant factors influencing resistivity properties.

• Journal of the Korean Vacuum Society
• /
• v.19 no.4
• /
• pp.307-313
• /
• 2010

One-dimensional cubic phase silicon carbide nanowires (${\beta}$-SiC NWs) were efficiently synthesized by thermal chemical vapor deposition (TCVD) with mixtures containing Si powders and nickel chloride hexahydrate $(NiCl_2{\cdot}6H_2O)$ in an alumina boat with a carbon source of methane $(CH_4)$ gas. SEM images are shown that the growth temperature (T) of $1,300^{\circ}C$ is not enough to synthesize the SiC NWs owing to insufficient thermal energy for melting down a Si powder and decomposing the methane gas. However, the SiC NWs could be synthesized at T>$1,300^{\circ}C$ and the most efficient temperature for growth of SiC NWs is T=$1,400^{\circ}C$. The synthesized SiC NWs have the diameter with an average range between 50~150 nm. Raman spectra clearly revealed that the synthesized SiC NWs are forming of a cubic phase (${\beta}$-SiC). Two distinct peaks at 795 and $970 cm^{-1}$ in Raman spectra of the synthesized SiC NWs at T=$1,400^{\circ}C$ represent the TO and LO mode of the bulk ${\beta}$-SiC, respectively. XRD spectra are also supported to the Raman spectra resulting in the strongest (111) peaks at $2{\Theta}=35.7^{\circ}$, which is the (111) plane peak position of 3C-SiC. Moreover, the gas flow rate of 300 sccm for methane is the optimal condition for synthesis of a large amount of ${\beta}$-SiC NW without producing the amorphous carbon structure shown at a high methane flow rate of 800 sccm. TEM images are shown two kinds of the synthesized ${\beta}$-SiC NWs structures. One is shown the defect-free ${\beta}$-SiC NWs with a (111) interplane distance of 0.25 nm, and the other is the stacking-faulted ${\beta}$-SiC NWs. Also, TEM images exhibited that two distinct SiC NWs are uniformly covered with $SiO_2$ layer with a thickness of less 2 nm.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.400-401
• /
• 2012

그래핀(Graphene)은 열 전도도가 높고 전자 이동도(200 000 cm2V-1s-1)가 우수한 전기적 특성을 가지고 있어 전계 효과 트랜지스터(Field effect transistor; FET), 유기 전자 소자(Organic electronic device)와 광전자 소자(Optoelectronic device) 같은 반도체 소자에 응용 가능하다. 그러나 에너지 밴드 갭이 없기 때문에 소자의 전기적 특성이 제한되는 단점이 있다. 최근에는 아크 방출(Arc discharge method), 화학적 기상 증착법(Chemical vapor deposition; CVD), 이온-조사법(Ion-irradiation) 등을 이용한 이종원자(Hetero atom)도핑과 화학적 처리를 이용한 기능화(Functionalization) 등의 방법으로 그래핀을 도핑 후 에너지 밴드 갭을 형성시키는 연구 결과들이 보고된 바 있다. 그러나 이러한 방법들은 표면이 균일하지 않고, 그래핀에 많은 결함들이 발생한다는 단점이 있다. 이러한 단점을 극복하기 위해 자가조립 단층막(Self-assembled monolayers; SAMs)을 이용하여 이산화규소(Silicon oxide; SiO2) 기판을 기능화한 후 그 위에 그래핀을 전사하면 그래핀의 일함수를 쉽게 조절하여 소자의 전기적 특성을 최적화할 수 있다. SAMs는 그래핀과 SiO2 사이에 부착된 매우 얇고 안정적인 층으로 사용된 물질의 특성에 따라 운반자 농도나 도핑 유형, 디락 점(Dirac point)으로부터의 페르미 에너지 준위(Fermi energy level)를 조절할 수 있다[1-3]. 본 연구에서는 SAMs한 기판을 이용하여 그래핀의 도핑 효과를 확인하였다. CVD를 이용하여 균일한 그래핀을 합성하였고, 기판을 3-Aminopropyltriethoxysilane (APTES)와 Borane-Ammonia(Borazane)을 이용하여 각각 아민 기(Amine group; -NH2)와 보론 나이트라이드(Boron Nitride; BN)로 기능화한 후, 그 위에 합성한 그래핀을 전사하였다. 기판 위에 NH2와 BN이 SAMs 형태로 존재하는 것을 접촉각 측정(Contact angle measurement)을 통해 확인하였고, 그 결과 NH2와 BN에 의해 그래핀에 도핑 효과가 나타난 것을 라만 분광법(Raman spectroscopy)과 X-선 광전자 분광법(X-ray photoelectron spectroscopy: XPS)을 이용하여 확인하였다. 본 연구 결과는 안정적이면서 패턴이 가능하기 때문에 그래핀을 기반으로 하는 반도체 소자에 적용 가능할 것이라 예상된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.113-114
• /
• 2009

Silicon carbide is one of the most attractive and promising wide band-gap semiconductor material with excellent physical properties and huge potential for electronic applications. Up to now, the most successful method for growth of large SiC crystals with high quality is the physical vapor transport (PVT) method [1, 2]. Since further reduction of defect densities in larger crystal are needed for the true implementation of SiC devices, many researchers are focusing to improve the quality of SiC single crystal through the process modifications for SiC bulk growth or new material implementations [3, 4]. It is well known that for getting high quality SiC crystal, source materials with high purity must be used in PVT method. Among various source materials in PVT method, a SiC powder is considered to take an important role because it would influence on crystal quality of SiC crystal as well as optimum temperature of single crystal growth, the growth rate and doping characteristics. In reality, the effect of powder on SiC crystal could definitely exhibit the complicated correlation. Therefore, the present research was focused to investigate the quality difference of SiC crystal grown by conventional PVT method with using various SiC powders. As shown in Fig. 1, we used three SiC powders with different particles size. The 6H-SiC crystals were grown by conventional PVT process and the SiC seeds and the high purity SiC source materials are placed on opposite side in a sealed graphite crucible which is surrounded by graphite insulation[5, 6]. The bulk SiC crystal was grown at $2300^{\circ}C$ of the growth temperature and 50mbar of an argon pressure. The axial thermal gradient across the SiC crystal during the growth is estimated in the range of $15\sim20^{\circ}C/cm$. The chemical etch in molten KOH maintained at $450^{\circ}C$ for 10 min was used for defect observation with a polarizing microscope in Nomarski mode. Electrical properties of bulk SiC materials were measured by Hall effect using van der Pauw geometry and a UV/VIS spectrophotometer. Fig. 2 shows optical photographs of SiC crystal ingot grown by PVT method and Table 1 shows electrical properties of SiC crystals. The electrical properties as well as crystal quality of SiC crystals were systematically investigated.

• Journal of IKEEE
• /
• v.20 no.4
• /
• pp.337-343
• /
• 2016

This study conducted the gamma ray spectroscopic analysis of the microcolumnar CsI:Tl deposited onto the SiPMs using thermal evaporation deposition. The SEM measured thickness of microcolumnar CsI:Tl and of its individual columns. From the SEM observation, the measured thickness of CsI:Tl were $450{\mu}m$ and $600{\mu}m$. The gamma ray spectroscopic properties of microcolumnar CsI:Tl, $450{\mu}m$ and $600{\mu}m$ thick deposited onto the SiPMs were analyzed using standard gamma ray sources $^{133}Ba$ and $^{137}Cs$. The spectroscopic analysis of microcolumnar CsI:Tl deposited onto the SiPMs included the measurements of response linearity over the $^{137}Cs$ gamma ray intensity; and gamma ray energy spectrum. Furthermore from the gamma ray spectrum measurement of $^{133}Ba$ and $^{137}Cs$, $450{\mu}m$ thick CsI:Tl showed good efficiency when measured with $^{133}Ba$ and $600{\mu}m$ thick CsI:Tl was highly efficient when measured with $^{137}Cs$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1999.07a
• /
• pp.122-122
• /
• 1999

Graphite with its advantages of high thermal conductivity, low thermal expansion coefficient, and low elasticity, has been widely used as a structural material for high temperature. However, graphite can easily react with oxygen at even low temperature as 40$0^{\circ}C$, resulting in CO2 formation. In order to apply the graphite to high temperature structural material, therefore, it is necessary to improve its oxidation resistive property. Silicon Carbide (SiC) is a semiconductor material for high-temperature, radiation-resistant, and high power/high frequency electronic devices due to its excellent properties. Conventional chemical vapor deposited SiC films has also been widely used as a coating materials for structural applications because of its outstanding properties such as high thermal conductivity, high microhardness, good chemical resistant for oxidation. Therefore, SiC with similar thermal expansion coefficient as graphite is recently considered to be a g행 candidate material for protective coating operating at high temperature, corrosive, and high-wear environments. Due to large lattice mismatch (~50%), however, it was very difficult to grow thick SiC layer on graphite surface. In theis study, we have deposited thick SiC thin films on graphite substrates at temperature range of 700-85$0^{\circ}C$ using single molecular precursors by both thermal MOCVD and PEMOCVD methods for oxidation protection wear and tribological coating . Two organosilicon compounds such as diethylmethylsilane (EDMS), (Et)2SiH(CH3), and hexamethyldisilane (HMDS),(CH3)Si-Si(CH3)3, were utilized as single source precursors, and hydrogen and Ar were used as a bubbler and carrier gas. Polycrystalline cubic SiC protective layers in [110] direction were successfully grown on graphite substrates at temperature as low as 80$0^{\circ}C$ from HMDS by PEMOCVD. In the case of thermal MOCVD, on the other hand, only amorphous SiC layers were obtained with either HMDS or DMS at 85$0^{\circ}C$. We compared the difference of crystal quality and physical properties of the PEMOCVD was highly effective process in improving the characteristics of the a SiC protective layers grown by thermal MOCVD and PEMOCVD method and confirmed that PEMOCVD was highly effective process in improving the characteristics of the SiC layer properties compared to those grown by thermal MOCVD. The as-grown samples were characterized in situ with OES and RGA and ex situ with XRD, XPS, and SEM. The mechanical and oxidation-resistant properties have been checked. The optimum SiC film was obtained at 85$0^{\circ}C$ and RF power of 200W. The maximum deposition rate and microhardness are 2$mu extrm{m}$/h and 4,336kg/mm2 Hv, respectively. The hardness was strongly influenced with the stoichiometry of SiC protective layers.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.434-435
• /
• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.

• Journal of IKEEE
• /
• v.20 no.3
• /
• pp.220-225
• /
• 2016

In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.11
• /
• pp.2075-2082
• /
• 2006

This paper presents modeling and optimization techniques for hish efficiency solar cell process on single-crystalline float zone (FZ) wafers. Among a sequence of multiple steps of fabrication, the followings are the most sensitive steps for the contact formation: 1) Emitter formation by diffusion; 2) Anti-reflection-coating (ARC) with silicon nitride using plasma-enhanced chemical vapor deposition (PECVD); 3) Screen-printing for front and back metalization; and 4) Contact formation by firing. In order to increase the performance of solar cells in terms of efficiency, the contact formation process is modeled and optimized using neural networks and genetic algorithms, respectively. This paper utilizes the design of experiments (DOE) in contact formation to reduce process time and fabrication costs. The experiments were designed by using central composite design which consists of 24 factorial design augmented by 8 axial points with three center points. After contact formation process, the efficiency of the fabricated solar cell is modeled using neural networks. Established efficiency model is then used for the analysis of the process characteristics and process optimization for more efficient solar cell fabrication.