• Journal of the Korean Ceramic Society
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• v.50 no.6
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• pp.359-363
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• 2013

Silicon carbide and its composites are being considered as a nuclear fuel cladding material for LWR nuclear reactors because they have a low neutron absorption cross section, low hydrogen production under accident conditions, and high strength at high temperatures. The SiC composite cladding tube considered in this study consists of three layers, monolith CVD SiC - $SiC_f$/SiC composite -monolith CVD SiC. The volume fraction of SiC fiber and surface roughness of the composite layer affect mechanical and corrosion properties of the cladding tube. In this study, various types of SiC fiber preforms with tubular shapes were fabricated by a filament winding method using two types of Tyranno SA3 grade SiC fibers with 800 filaments/yarn and 1600 filaments/yarn. After chemical vapor infiltration of the SiC matrix, the surface roughness and fiber volume fraction were measured. As filament counts were changed from 800 to 1600, the surface roughness increased but the fiber volume fraction decreased. The $SiC_f$/SiC composite with a bamboo-like winding pattern has a smaller surface roughness and a higher fiber volume fraction than that with a zigzag winding pattern.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.5-12
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• 2000

As a semiconductor material for electronic devices operated under extreme environmental conditions, silicon carbides (SiCs) have been intensively studied because of their excellent electrical, thermal and other physical properties. The growth characteristics of single- crystalline 6H-SiC homoepitaxial layers grown by a thermal chemical vapor deposition (CVD) were investigated. Especially, the successful growth condition of 6H-SiC homoepitaxial layers using a SiC-uncoated graphite susceptor that utilized Mo-plates was obtained. The CVD growth was performed in an RF-induction heated atmospheric pressure chamber and carried out using off-oriented ($3.5^{\circ}$tilt) substrates from the (0001) basal plane in the <110> direction with the Si-face side of the wafer. In order to investigate the crystallinity of grown epilayers, Nomarski optical microscopy, transmittance spectra, Raman spectroscopy, XRD, Photoluninescence (PL) and transmission electron microscopy (TEM) were utilized. The best quality of 6H-SiC homoepitaxial layers was observed in conditions of growth temperature $1500^{\circ}C$ and C/Si flow ratio 2.0 of $C_3H_8$ 0.2 sccm & $SiH_4$ 0.3 sccm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.816-820
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• 2013

We investigated the characteristics of the silicon oxy-nitride and nitride films grown by plasma-enhanced chemical vapor deposition (PECVD) at the low temperature with a varying $NH_3/N_2O$ mixing ratio and a fixed $SiH_4$ flow rate. The deposition temperature was held at $150^{\circ}C$ which was the temperature compatible with the plastic substrate. The composition and bonding structure of the nitride films were investigated using Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS). Nitrogen richness was confirmed with increasing optical band gap and increasing dielectric constant with the higher $NH_3$ fraction. The leakage current density of the nitride films with a high NH3 fraction decreased from $8{\times}10^{-9}$ to $9{\times}10^{-11}(A/cm^2$ at 1.5 MV/cm). This results showed that the films had improved electrical properties and could be acceptable as a gate insulator for thin film transistors by deposited with variable $NH_3/N_2O$ mixing ratio.

• Bulletin of the Korean Chemical Society
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• v.31 no.12
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• pp.3593-3599
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• 2010

In an original effort, this lab attempted to employ polystyrene nanoparticles as a template for the synthesis of ordered and highly porous macroporous $SiO_2$ thin films, utilizing their high combustion temperature and narrow size distribution. However, polystyrene nanoparticle thin films were not obtained due to the low interaction between individual particles and between the particle and silicon substrate. However, polystyrene-polyacrylic acid (PS-AA) colloidal particles of a core-shell structure were synthesized by a one-pot miniemulsion polymerization approach, with hydrophilic polyacrylic acid tails on the particle surface that improved interaction between individual particles and between the particle and silicon substrate. The PS-AA thin films were spin-coated in the thickness ranges from monolayer to approximately $1.0\;{\mu}m$. Using the PS-AA thin films as sacrificial templates, macroporous $SiO_2$ thin films were successfully synthesized by vapor deposition or conventional solution sol-gel infiltration methods. Inspection with field emission scanning electron microscopy (FE-SEM) showed that the macroporous $SiO_2$ thin films consist of interconnected air balls (~100 nm). Typical macroporous $SiO_2$ thin films showed ultralow refractive indices ranging from 1.098 to 1.138 at 633 nm, according to the infiltration conditions, which were confirmed by spectroscopy ellipsometry (SE) measurements. This research shows how the synthetic control of the macromolecule such as hydrophilic polystyrene nanopaticles and silicate sol precursors innovates the optical properties and processabilities for actual applications.

• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.3
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• pp.245-248
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• 2020

The wettability of silicon carbide (SiC) crystal, which has 6H-SiC and 4H-SiC regions prepared using the physical vapor transport (PVT) method, is quantitatively analyzed using dispensed deionized (DI) water droplets. Regardless of the polytypes in SiC, the average of five contact angle measurements showed a difference of about 6° between the Si-face and C-face. The contact angle on the Si-face (C-face) is measured after the removal of the native oxide using BOE (6:1), and revealed a significant decrease of the contact angle from 74.9° (68.4°) to 47.7° (49.3°) and from 75.8° (70.2°) to 51.6° (49.5°) for the 4H-SiC and 6H-SiC regions, respectively. The contact angle of the Si-face recovered over time during room temperature oxidation in air; in contrast, that of the C-face did not recover to the initial value. This study shows that the contact angle is very sensitive to SiC surface polarity, specific surface conditions, and process time. Contact angle measurements are expected to be a rapid way of determining the surface polarity and wettability of SiC crystals.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.74-74
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• 2000

낮은 유전상수(k$\leq$3)와 높은 열적안정성(>4$25^{\circ}C$)은 초고집적회로(ULSI)기술에서 RC 지연을 해결하기 위한 금속배선의 중간 절연층으로서의 2개의 가장 중요한 특성이다. 본 연구에서는 cyclohezane을 precursor로 사용하여 plasma enhanced chemical vapor deposition(PECVD)방법으로 유기박막을 성장시켰으며 낮은 유전상수와 높은 열적안정성을 동시에 확보하기 위하여 열적안정성은 좋지 않지만 유전상수가 낮은 박막(soft layer)위에 유전상수는 다소 높지만 열적안정성이 좋은 박막(hard layer)을 얇게 증착하여 hard layer/soft layer의 2층 구조를 형성하여서 구조적, 전기적 특성을 조사하였다. 유기박막은 5$0^{\circ}C$로 유지된 reactor 내부에서 argon(Ar) plasma에 의해 증착되었으며 platinum(Pt)기판과 silicon 기판위에 동시에 증착하였다. Pt 기판위에 증착한 시편으로 유전상수, I-V 등 전기적 특성을 측정하였고, silicon 기판위에 증착한 시편으로 열적안정성과 구조적 특성등을 분석하였다. 증착압력 0.2Torr에서 plasma power를 5W에서90W로 증가할 때 유전상수는 2.36에서 3.39로 증가하였으며 열적안정성은 90W에서 180W로 증가하였을 때 유전상수는 2.42에서 2.79로 증가하엿고 열적안정성은 모두30$0^{\circ}C$이하였다. 단일층 구조에서는 유전상수가 낮은 박막은 열적으로 불안정하고 열적 안정성이 좋은 박막은 유전상수가 다소 높은 문제가 나타났다. 이런 문제를 해결하기 위하여 2 Torr, 120W에서 증착한 유전상수가 2.55이고 열적으로 불안정한 박막을 soft layer로 5150 증착하고 그 위에 0.2Torr, 90W에서 증착한 유전상수가 3.39이고 열적으로 45$0^{\circ}C$까지 안정한 박막을 hard layer로 360 , 720 , 1440 증착하였다. 증착된 2층구조 박막의 유전상수는 각각 2.62, 2.68, 2.79이었으며 열적안정성 측정에서는 40$0^{\circ}C$까지 두께 감소가 보이지 않았다. 그러나 SEM 측정에서 열처리 후 표면이 거칠어지는 현상이 발견되었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.447-447
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• 2010

일찍이 $SiO_2$ (Silicon dioxide) 박막은 다양한 분야에서 유전층, 부식 방지층, passivation층 등의 역할을 해왔다. 그리고 이러한 박막 공정은 대부분 진공의 환경에서 그 공정이 이루어지고 있다. 하지만 이러한 진공 system은 chamber, loadlock 그리고 펌프 등의 다양한 진공장비로 인한 생산 비용 증가, 공정의 복잡성뿐만 아니라 공정의 대면적화에 어려움을 지니고 있다. 그리고 최근 flexible display의 제조 공정에서 polymer 혹은 plastic 기판을 제조 공정에 적용시키기 위해 저온 공정이 필수적으로 요구 되고 있다. 이러한 기술적 한계를 뛰어 넘기 위해 최근 많은 연구가들은 atmospheric pressure plasma enhanced chemical vapor deposition (AP-PECVD)에 대해 지속적으로 다양한 연구를 하고 있다. 본 연구에서는 remote-type의 modified pin-to-plate dielectric barrier discharge (DBD) 시스템을 이용한 $SiO_2$ 무기 박막 증착에 관해 연구하였다. $O_2$/He/Ar의 gas와 5 kV AC power (30 kHz)의 전원장치를 통해 고밀도 대기압 플라즈마를 발생시켰고, silicon precursor로는 hexamethyldisilazane (HMSD)를 사용하였다. 먼저 HMDS와 $O_2$ gas의 flow rate 변화에 따른 증착률을 조사하였고 그 다음으로 박막의 조성 및 표면 특성을 조사하였다. HMDS의 유량이 100 ~ 300 sccm으로 증가함에 따라 증착속도는 증가했다. 하지만 FT-IR을 통해 HMDS의 유량이 증가하면 반응에 참여할 산소 분자의 부족으로 인해 $-(CH_3)_X$의 peak intensity가 증가하고, -OH의 peak intensity가 점차 감소함을 관찰 할 수 있었다. 또한 증착된 박막의 표면에 particle과 불균일한 surface morphology 등을 SEM image를 통해 관찰 하였다. 산소 유량이 탄소와 관련된 많은 불순물들의 제거에 도움이 됨에도 불구하고 14 slm 이상의 산소가 반응기 내로 주입되게 되면 대기압 플라즈마의 discharge가 불안정하게 되어 공정효율을 저하시키는 요소가 되었다. 결과적으로 HMDS (150 sccm)/$O_2$ (14 slm)/He (5 slm)/Ar (3 slm)의 조건에서 약 42.7 nm/min 증착률을 가지며, 불순물이 적고 surface morphology가 깨끗한 $SiO_2$ 박막을 증착할 수 있었다.

• Proceedings of the SAREK Conference
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• 2008.11a
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• pp.170-174
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• 2008

Recently, a problem related to the thermal management in portable electronic and telecommunication devices is becoming issued. That is due to the trend of slimness of the devices, so it is not easy to find the optimal thermal management technology for the devices. From now on, a pressed circular type cooling device has been mainly used, however the cooling device with thin thickness is becoming needed by the inner space constraint. In the present study, the silicon and metal flat plate type cooling device with the separated vapor and liquid flow path was designed and fabricated. Through the experimental study, the normal isothermal characteristic by vapor-liquid phase change was confirmed and the cooling device with 70mm of total length showed 6.8W of the heat transfer rate within the range of $4{\sim}5^{\circ}C$/W of thermal resistance. In the meantime, the metal cooling device was developed for commercialization. The device was designed to have all structures of evaporator, vapor flow path, liquid flow path and condenser in one plate. And an envelope of that could be completed by combining the two plates of same structure and size. And the simplicity of fabrication process and reduction of manufacturing cost could be accomplished by using the stamping technology for fabricating large flow paths relatively. In the future, it will be possible to develop the commercialized cooling device by revising the fabrication process and enhancing the thermal performance of that.