• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.85-94
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• 1994

A high-resolution transmission electron microscopy study of the solid phase crystallization of the amorphous silicon thin films, deposited on SiOS12T at 52$0^{\circ}C$ by low pressure chemical vapor deposition and annealed at 55$0^{\circ}C$ in a dry N$_{2}$ ambient was carried out so that the arrangement of atoms in the crystalline silicon and at the amorphous/crystalline interface of the growing grains could be understood on an atomic level. Results show that circular crystalline silicon nuclei have formed and then the grains grow to an elliptical or dendritic shape. In the interior of all the grains many twins whose{111} coherent boundaries are parallel to the long axes of the grains are observed. From this result, it is concluded that the twins enhance the preferential grain growth in the <112> direction along {111} twin planes. In addition to the twins. many defect such as intrinsic stacking faults, extrinsic stacking faults, and Shockley partial dislocations, which can be formed by the errors in the stacking sequence or by the dissociation of the perfect dislocation are found in the silicon grain. But neither frank partial dislocations which can be formed by the condensation of excess silicon atoms or vacancies and can form stacking fault nor perfect dislocations which can be formed by the plastic deformation are observed. So it is concluded that most defects in the silicon grain are formed by the errors in the stacking sequence during the crystallization process of the amorphous silicon thin films.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.108-112
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• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 90 % of the market, despite the development of a variety of thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon photovoltaic remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner thickness of silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials of different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With lower paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 130 micron thickness of the wafer even though the conversion efficiency decrease of 0.5 % occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al paste application.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.198.1-198.1
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• 2016

Organic light-emitting diode (OLED) displays have promising potential to replace liquid crystal displays (LCDs) due to their advantages of low power consumption, fast response time, broad viewing angle and flexibility. Organic light emitting materials are vulnerable to moisture and oxygen, so inorganic thin films are required for barrier substrates and encapsulations.[1-2]. In this work, the silicon-based inorganic thin films are deposited on plastic substrates by plasma-enhanced chemical vapor deposition (PECVD) at low temperature. It is necessary to deposit thin film at low temperature. Because the heat gives damage to flexible plastic substrates. As one of the transparent diffusion barrier materials, silicon oxides have been investigated. $SiO_x$ have less toxic, so it is one of the more widely examined materials as a diffusion barrier in addition to the dielectric materials in solid-state electronics [3-4]. The $SiO_x$ thin films are deposited by a PECVD process in low temperature below $100^{\circ}C$. Water vapor transmission rate (WVTR) was determined by a calcium resistance test, and the rate less than $10.^{-2}g/m^2{\cdot}day$ was achieved. And then, flexibility of the film was also evaluated.

• Journal of the Korean institute of surface engineering
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• v.34 no.5
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• pp.503-509
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• 2001

Thin films of hydrogenated amorphous silicon (a-Si : H) and hydrogenated amorphous silicon carbide (a-SiC:H) of different compositions were deposited on Si(100) wafer and glass by RF plasma-enhanced chemical vapor deposition (RF-PECVD). In the present work, we have investigated the effects of the RF power on the properties, such as optical band gap, transmittance and crystallinity. The Raman data show that the a-Si:H material consists of an amorphous and crystalline phase for the co-presence of two peaks centered at 480 and $520 cm^{-1}$ . The UV-VIS data suggested that the optical energy band gap ($E_{g}$ ) is not changed effectively with RF power and the obtained $E_{g}$(1.80eV) of the $\mu$c-Si:H thin film has almost the same value of a-Si:H thin film (1.75eV), indicating that the crystallity of hydrogenated amorphous silicon thin film can mainly not affected to their optical properties. However, the experimental results have shown that$ E_{g}$ of the a-SiC:H thin films changed little on the annealing temperature while $E_{g}$ increased with the RF power. The Raman spectrum of the a-SiC:H thin films annealed at high temperatures showed that graphitization of carbon clusters and microcrystalline silicon occurs.

• Journal of the Korean institute of surface engineering
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• v.26 no.3
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• pp.115-120
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• 1993

Aluminum thin films were deposited on the silicon substrate by the pyrolysis of TrilsoButylAluminum (TIBA) in a cold wall LPCVD reactor. The effect of substrate on the surface topograply and the decomposition reaction was investigated. The activation energy for the decomposition of TIBA was turned out to be 1 eV from the Arrhenious plot. The surface topography of the CVD aluminum could be improved by the application of thin metal film, which was in-situ deposited on the silicon prior to CVD process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.7
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• Transactions on Electrical and Electronic Materials
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• v.5 no.2
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• pp.41-49
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• 2004

Layer transfer process has emerged as a promising tool in the field of thin silicon solar cell technology. This process can use mono-crystalline silicon as a surface for the epitaxial growth of a thin layer of silicon. It requires some sort of surface conditioning of the substrate due to which the surface become suitable for homo-epitaxy and lift off after solar cell fabrication. The successful reuse of substrate has been reported. The use of the conditioned surface without any kind of epitaxial layer growth is also the issue to be addressed. This review paper basically describes the five most cost effective methods on which works are in progress. Several types of possible problems envisaged by different research groups are also incorporated here with necessary discussion. Work in Korea has already started in this area in collaboration IC Design and Fabrication Centre, Jadavpur University, India and that also has been mentioned.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.113-116
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• 2005

In this paper, silicon thin-film solar cells(Si- TFSC) and a-Si/c-Si heterojunction solar cells(HJ-cell) are investigated. The Si-TFSC was prepared on glass substrate by depositing $1-3{\mu}m$ thin-film silicons by glow discharge method. The $a-Si:H/{\mu}c-Si:H$ tandem solar cells on textured ZnO:A1 TCO (transparent conducting oxide) showed improved Jsc in top and bottom cells than that on $SnO_2:F$ TCO. This enhancement of jsc resulted from improved light trapping effect by front textured ZnO:A1. The a-Si/c-Si HJ-cells with simple structure without high efficiency features are suffering from low Voc and Jsc. The improvement of front nip and back interface properties by adopting high quality silicon-films at low temperature should be done both for increasing device performances and production cost.

• Korean Journal of Materials Research
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• v.30 no.4
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• pp.169-175
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• 2020

Silicon nitride thin films are deposited by RF (13.57 MHz) magnetron sputtering process using a Si (99.999 %) target and with different ratios of Ar/N₂ sputtering gas mixture. Corning G type glass is used as substrate. The vacuum atmosphere, RF source power, deposit time and temperature of substrate of the sputtering process are maintained consistently at 2 ~ 3 × 10^-3 torr, 30 sccm, 100 watt, 20 min. and room temperature, respectively. Cross sectional views and surface morphology of the deposited thin films are observed by field emission scanning electron microscope, atomic force microscope and X-ray photoelectron spectroscopy. The hardness values are determined by nano-indentation measurement. The thickness of the deposited films is approximately within the range of 88 nm ~ 200 nm. As the amount of N₂ gas in the Ar:N₂ gas mixture increases, the thickness of the films decreases. AFM observation reveals that film deposited at high Ar:N₂ gas ratio and large amount of N₂ gas has a very irregular surface morphology, even though it has a low RMS value. The hardness value of the deposited films made with ratio of Ar:N₂=9:1 display the highest value. The XPS spectrum indicates that the deposited film is assigned to non-stoichiometric silicon nitride and the transmittance of the glass with deposited SiO₂-Si_xN_y thin film is satisfactory at 97 %.

• Transactions on Electrical and Electronic Materials
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• v.16 no.1
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• pp.10-15
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• 2015

A thin-film transmission line (TFTL) employing a microstrip line/coplanar waveguide (ML/CPW) was fabricated on a silicon substrate for application to a miniaturized on-chip RF component, and the RF characteristics of the device with the proposed structure were investigated. The TFTL employing a ML/CPW composite structure exhibited a shorter wavelength than that of a conventional coplanar waveguide and that of a thin-film microstrip line. When the TFTL with the proposed structure was fabricated to have a length of ${\lambda}/8$, it showed a loss of less than 1.12 dB at up to 30 GHz. The improvement in the periodic capacitance of the TFTL caused for the propagation constant, ${\beta}$, and the effective permittivity, ${\varepsilon}_{eff}$, to have values higher than those of a device with only a conventional coplanar waveguide and a thin film microstrip line. The TFTL with the proposed structure showed a ${\beta}$ of 0.53~2.96 rad/mm and an ${\varepsilon}_{eff}$ of 22.3~25.3 when operating from 5 to 30 GHz. A highly miniaturized impedance transformer was fabricated on a silicon substrate using the proposed TFTL for application to a low-impedance transformation for broadband. The size of the impedance transformer was 0.01 mm2, which is only 1.04% of the size of a transformer fabricated using a conventional coplanar waveguide on a silicon substrate. The impedance transformer showed excellent RF performance for broadband.