• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.3
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• pp.882-890
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• 1996

Mechanical properties, including Young's modulus, residual stress and rupture strength, of a thermally evaporated gold film have been measured form a blister test. In a theoretical study, the priniple of minimum potential energy and that of virtual work have been applied to the pressurized circular membrane problem, and load-deflection relations have been derived for typical membrane deflection mode of spheroidal shape. In an experimental study, circular gold membranes of 4800 A-thickness and 3.5mm diameter were fabricated by the silicon electropolishing technique. Mecahnical properties of the thin gold films were deduced from the load-deflection curves obtained by the blister test, Young's moduli, obtianed from blister test, have been in the range of 45-70 GPa, while those of bulk gold have been in the range of 78-80 GPa. Residual stresses in the evaporated gold films have been measured as 28-110MPa in tension, The rupture strength of the gold film has turned out to be almost equal to that of dental gold alloy (310-380MPa). It has been demonstrated that the present specimen fabrication method and blister test apparatus have been effective for simultaneous measurement of Young's modulus, residual stress and repture strength of thin solid films. Especially, the electropolishing technique employed here has provided a simple and practical way to fabricate thin membranes in a circular or an arbitrary shape, which could not be obtained by the conventional anisotropic silicon mecromachining technique.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.285-291
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• 2013

In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.05a
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• pp.96-99
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• 1993

Electrical properties of the Thin Film Transistor(TFT) electrode metal films were investigated through the Test Elements Group(TEG) experiment. The main purpose of this investigation was to characterize the electrical resistance properties of patterned metal films with respect to the variations of film thickness and TEG metal line width. Aluminum(Al), Tantalum(Ta) and Chromium(Cr) that are currently used as TFT electrode films were selected as the probed metal films. To date, no work in the electrical characterizations of patterned electrodes of a-Si TFT was accomplished. Bulk resistance$(R_b)$, sheet resistance$(R_s)$, and resistivities($\rho$) of TEG patterned metal lines were obtained. Electrical continuity test of metal film lines was also performed in order to investigate the stability of metallization process. Almost uniform-linear variations of the electrical properties with respect to the metal line displacements was also observed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.3 s.94
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• pp.253-259
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• 2005

In this paper, BaSrTiO$_{3}$(BST) thin film tunable interdigital capacitor using low cost silicon substrate instead of expensive single-crystalline substrate is presented. The tunable capacitor in which BST thin film is deposited by PLD has operation frequency and applied bias up to 4 GHz and 50 V, respectively. The maximum tunability in capacitance is found to be 30$\%$, for an applied field of 5 kV/cm at a bias of 50 V. Therefore, it has been shown that the BST microwave tunable capacitor can be integrated onto Si substrate.

• Biotechnology and Bioprocess Engineering:BBE
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• v.11 no.5
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• pp.455-461
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• 2006

In this study, we have described a method for the fabrication of a protein chip on silicon substrate using hydrophobic thin film and microfluidic channels, for the simultaneous detection of multiple targets in samples. The use of hydrophobic thin film provides for a physical, chemical, and biological barrier for protein patterning. The microfluidic channels create four protein patterned strips on the silicon surfaces with a high signal-to-noise ratio. The feasibility of the protein chips was determined in order to discriminate between each protein interaction in a mixture sample that included biotin, ovalbumin, hepatitis B antigen, and hepatitis C antigen. In the fabrication of the multiplexed assay system, the utilization of the hydrophobic thin film and the microfluidic networks constitutes a more convenient method for the development of biosensors or biochips. This technique may be applicable to the simultaneous evaluation of multiple protein-protein interactions.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• Journal of the Korean Vacuum Society
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• v.12 no.2
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• pp.130-135
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• 2003

Polycrystalline silicon thin films have been used for low cost thin film device application. However, it was very difficult to fabricate high performance poly-Si at a temperature lower than $600^{\circ}C$ for glass substrate because the crystallization process technologies like conventional solid phase crystallization (SPC) require the number of high temperature (600-$1000^{\circ}C$) process. The objective of this paper is to grow poly-Si on flexible substrate using a rapid thermal crystallization (RTC) of amorphous silicon (a-Si) layer and make the high temperature process possible on molybdenum substrate. For the high temperature poly-Si growth, we deposited the a-Si film on the molybdenum sheet having a thickness of 150 $\mu\textrm{m}$ as flexible and low cost substrate. For crystallization, the heat treatment was performed in a RTA system. The experimental results show the grain size larger than 0.5 $\mu\textrm{m}$ and conductivity of $10^{-5}$ S/cm. The a-Si was crystallized at $1050^{\circ}C$ within 3min and improved crystal volume fraction of 92 % by RTA. We have successfully achieved a field effect mobility over 67 $\textrm{cm}^2$/Vs.

• Korean Journal of Materials Research
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• v.9 no.9
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• pp.890-895
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• 1999

The recent important issue in solar cell fabrication is to adopt thin film silicon solar cells on cheap substrates. However, thin cells demand new grid design concept that all the contacts(to the emitter and base) be located on the front surface. Hence, the aim of the investigation presented in this paper was to determine the potential and the basic limitation of the design. With this concept, an interdigitated front grid structure was realized and cells were fabricated through a set of photolithography processes. Confirmed efficiencies of up to 11.5% were achieved on bonded SOI wafers with a cell thickness of 50$\mu\textrm{m}$ in the case of finger spacing more than $\mu\textrm{m}$ and a base width of 35$\mu\textrm{m}$. It was also shown from the results that the design rules for optimizing the base fraction and reducing the shadowing fraction are noted as an important technique to realize high-efficiency thin silicon solar cells.

• Current Photovoltaic Research
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• v.3 no.3
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• pp.80-84
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• 2015

We suggest new emitter formation method using solid-phase epitaxy (SPE); solid-phase epitaxy emitter (SEE). This method expect simplification and cost reduction of process compared with furnace process (POCl3 or BBr3). The solid-phase epitaxy emitter (SEE) deposited a-Si:H layer by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD) on substrate (c-Si), then thin layer growth solid-phase epitaxy (SPE) using rapid thermal process (RTP). This is possible in various emitter profile formation through dopant gas ($PH_3$) control at deposited a-Si:H layer. We fabricated solar cell to apply solid-phase epitaxy emitter (SEE). Its performance have an effect on crystallinity of phase transition layer (a-Si to c-Si). We confirmed crystallinity of this with a-Si:H layer thickness and annealing temperature by using raman spectroscopy, spectroscopic ellipsometry and transmission electron microscope. The crystallinity is excellent as the thickness of a-Si layer is thin (~50 nm) and annealing temperature is high (<$900^{\circ}C$). We fabricated a 16.7% solid-phase epitaxy emitter (SEE) cell. We anticipate its performance improvement applying thin tunnel oxide (<2nm).