• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1051-1054
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• 2009

This paper investigates approaches for improving effective mobility of organic thin film transistors (OTFTs). We consider gate dielectric optimization, whereby we demonstrated >2x increase in mobility by using a silicon-rich silicon nitride ($SiN_x$) gate dielectric for polythiophene-based (PQT) OTFTs. We also engineer the dielectric-semiconductor ($SiN_x$-PQT) interface to attain a 27x increase in mobility (up to 0.22 $cm^2$/V-s) using an optimized combination of oxygen plasma and OTS SAM treatments. Augmentative material systems by combining 1-D nanomaterials (e.g., carbon nanotubes, zinc oxide nanowires) in an organic matrix for nanocomposite OTFTs provided a further boost in device performance.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1483-1485
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• 2009

Silicon dioxide ($SiO_2$) thin films were deposited using a modified DBD called a "pin-to-plate-type DBD" in order to generate high-density plasmas with a gas mixture of PDMS/$O_2$. The effect of the gas mixture on the physical and chemical properties of $SiO_2$ deposited by the pin-to-plate-type DBD with the mixture of PDMS/$O_2$ was investigated.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.566-567
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• 2009

We have examined the silicon nitride ($SiN_x$) as gate insulator with the ammonia ($NH_3$) plamsa treatment for the soluble derivatives of polythiophene as p-type channel materials of organic thin film transistors (OTFTs). Fabrications of the jetting-processed OTFTs with $SiN_x$ as gate insulator by $NH_3$ plasma treatment can be similar to performance of OTFTs with silicon dioxide ($SiO_2$) insulator.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.417-420
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• 2007

A 12k-bit SRAM has been developed for line memory of system-on-glass (SoG) with lowtemperature poly-silicon (LTPS) thin film transistor (TFT). For accurate sensing even with the large variation and mismatches in the characteristics of LTPS TFT, mismatch immune sense amplifier is developed. The SRAM shows 30ns read access time with 7V supply voltage while dissipating 4.05mW and 1.75mW for write and read operation, respectively

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.7
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• pp.1121-1127
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• 1994

The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the thrshold voltage shifts of a-Si:H TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the stressing periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si:H TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

• Electrical & Electronic Materials
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• v.9 no.10
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• pp.1008-1012
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• 1996

I-V, C-V characteristics of inverted staggered type hydrogenerated amorphous silicon thin film transistor(a-Si:H TFT) was studied and experimentally verified. The results show that the log-log plot of drain current increased by voltage increase. The saturated drain current of DC output characteristics increased at a fixed gate voltage. According to the increase of gate voltage, activation energy of electron and the increasing width of Id at high voltage were decreased. Id saturation current saturated at high Vd over 4.5V, Vg-ld hysteresis characteristic curves occurred between -15V and 15V of Vg. Hysteresis current decreased at low voltage of -15V and increased at high voltage of 15V.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.429-432
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• 1987

A new LOCOS (Local Oxidation of Silicon) process using a thin nitride film directly deposited on the silicon substrate by LPCVD has been developed in order to reduce the bird's beak length. SEM studies showed that nitride thickness of 50nm can decrease the bird's beak length down to 0.2um with 450nm field oxide. No crystalline defects are observed around the bird's beak after the Wright etch. A 30% improvement in current density was obtained when this new method was applied to MOS transistors (W/L*2.9/20.4) compared to conventional LOCOS process (bird's beak length=0.7um). Other various electrical parameters improved by this new simple LOCOS process are reported in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1115-1121
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• 1998

MLS capacitor with lipid ultra thin films were deposited by Langmuir-Blodgett (LB) method on the silicon wafer. The current versus voltage and capacitance versus voltage relationships are depend on the applied voltage, electrode area and electrode materials. LB films deposited were made of L-$\alhpa$-DLPC, the 1 layer’s thickness of 35${\AA}$ was measured by ellipsometer. And MLS capacitor with different electrode materials, the work function of these materials was investigated to increase the leakage current. The result indicated the lower leakage current and very high saturation value of capacitance was reached within 700-800 pF when the two electrode was Ag. And $\varepsilon$1, $\varepsilon$2 versus photon energy showed good film formation.

• Journal of Sensor Science and Technology
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• v.20 no.4
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• pp.260-265
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• 2011

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.