• 한국표면공학회지
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• 제37권1호
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• pp.22-27
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• 2004

Copper electroforming process has been applied to duplicate Koryo Tripitaka (Taejang'kyong), wooden printing block. Thin copper replica printing plates of 1 mm thickness was successfully manufactured from the printing face (54.5${\times}$25.5 cm) of wooden printing plate. Major processes are (1) silicon rubber replication of the master (2) silvering on silicon rubber (3) copper electroforming (4) separation of copper from the silicon mandrel (5) final coloring by brass plating and trimming. This process has various Potential applications in making thin metallic objects such as plaques, statues, bust and hollow metal objects for jewelry.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 전기화학회지
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• 제7권4호
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• pp.173-178
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• 2004

플라즈마 화학 기상 증착법으로 구리 막$(foil,\;35{\mu}m)$표면 위에 $SiH_4$와 Ar혼합가스를 공급하여 실리콘 박막을 증착 한 후 리튬 이온전지의 음극으로 활용하였다. 증착 온도에 따라 비정질 실리콘 박막과 copper silicide박막 형태의 다른 두 종류의 실리콘 박막 구조가 형성되는 것이 관찰되었다. $200^{\circ}C$ 이하의 온도에서는 비정질 실리콘 박막이 증착되었고, $400^{\circ}C$ 이상의 온도에서는 실리콘 라디칼과 확산된 구리 이온의 반응에 의한 그래뉼러 형태의 copper silicide박막이 형성되었다. 비정질 실리콘 박막은 copper silicide박막 보다 높은 용량을 나타냈으나 충·방전 반응에 의한 급격한 용량 손실을 나타냈다. 이것은 비정질 실리콘 박막의 부피 팽창에 의한 것으로 추정된다. 그러나 copper silicide 박막을 음극으로 사용했을 때는 copper silicide를 형성한 실리콘과 구리의 화학결합이 막 구조의 부피변화를 감소 시켜줄 뿐 아니라 낮은 전기 저항을 갖기 때문에 싸이클 특성이 향상되었다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2005년도 제17회 워크샵 및 추계학술대회
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• pp.561-566
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• 2005

Polycrystalline silicon films were deposited using hot wire CVD (HWCVD). The deposition of silicon thin films was approached by the theory of charged clusters (TCC). The TCC states that thin films grow by self-assembly of charged clusters or nanoparticles that have nucleated in the gas phase during the normal thin film process. Negatively charged clusters of a few nanometer in size were captured on a transmission electron microscopy (TEM) grid and observed by TEM. The negatively charged clusters are believed to have been generated by ion-induced nucleation on negative ions, which are produced by negative surface ionization on a tungsten hot wire. The electric current on the substrate carried by the negatively charged clusters during deposition was measured to be approximately $-2{\mu}A/cm^2$. Silicon thin films were deposited at different $SiH_4$ and $H_2$ gas mixtures and filament temperatures. The crystalline volume fraction, grain size and the growth rate of the films were measured by Raman spectroscopy, X-ray diffraction and scanning electron microscopy. The deposit ion behavior of the si1icon thin films was related to properties of the charged clusters, which were in turn controlled by the process conditions. In order to verify the effect of the charged clusters on the growth behavior, three different electric biases of -200 V, 0 V and +25 V were applied to the substrate during the process, The deposition rate at an applied bias of +25 V was greater than that at 0 V and -200 V, which means that the si1icon film deposition was the result of the deposit ion of charged clusters generated in the gas phase. The working pressures had a large effect on the growth rate dependency on the bias appled to the substrate, which indicates that pressure affects the charging ratio of neutral to negatively charged clusters. These results suggest that polycrystalline silicon thin films with high crystalline volume fraction and large grain size can be produced by control1ing the behavior of the charged clusters generated in the gas phase of a normal HWCVD reactor.

• 한국진공학회지
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• 제12권4호
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• pp.263-268
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• 2003

차세대 반도체 및 디스플레이 소자에 적용되는 실리콘 질화막은 정확한 두께 제어와 우수한 물성을 필요로 한다. 본 연구에서는 우수한 특성의 실리콘 질화막을 형성하기 위해 Si 원료물질로 $SiC1_4$, N 원료물질로 $NH_3$을 사용하고 $500^{\circ}C$에서 $600^{\circ}C$ 온도구간에서 batch-type 장비를 이용하여 원자층 증착 방법으로 박막을 형성하고 증착된 박막의 특성을 살펴보았다. Batch-type 장비를 사용한 박막의 증착은 표면반응에 의한 균일한 원자층 증착임을 확인하였으며, 증착 cycle의 횟수를 조절하여 원하는 두께의 박막을 형성할 수 있었다. 원자층 증착된 박막의 조성, 굴절률 및 습식각 속도를 기존의 저압화학증착 방법에 의해 증착된 박막과 비교한 결과, 원자층 증착 방법을 사용하여 기존의 방법보다 증착온도를 $250^{\circ}C$ 이상 낮추면서도 유사한 물성을 가진 박막을 형성할 수 있음을 확인하였다. Pyridine을 촉매로 첨가하여 원자층 증착한 박막의 경우에는 증착속도를 50% 가량 향상시킬 수 있었으나 박막의 구조가 불안정하여 쉽게 산화되므로 반도체나 디스플레이 소자 제조에 적용하기에는 부적절한 것으로 판단된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• 한국재료학회지
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• 제22권1호
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• pp.8-15
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• 2012

Silicon-based thin film was prepared at room temperature by an electrochemical deposition method and a feasibility study was conducted for its use as an anode material in a rechargeable lithium battery. The growth of the electrodeposits was mainly concentrated on the surface defects of the Cu substrate while that growth was trivial on the defect-free surface region. Intentional formation of random defects on the substrate by chemical etching led to uniform formation of deposits throughout the surface. The morphology of the electrodeposits reflected first the roughened surface of the substrate, but it became flattened as the deposition time increased, due primarily to the concentration of reduction current on the convex region of the deposits. The electrodeposits proved to be amorphous and to contain chlorine and carbon, together with silicon, indicating that the electrolyte is captured in the deposits during the fabrication process. The silicon in the deposits readily reacted with lithium, but thick deposits resulted in significant reaction overvoltage. The charge efficiency of oxidation (lithiation) to reduction (delithiation) was higher in the relatively thick deposit. This abnormal behavior needs to clarified in view of the thickness dependence of the internal residual stress and the relaxation tendency of the reaction-induced stress due to the porous structure of the deposits and the deposit components other than silicon.

• Bulletin of the Korean Chemical Society
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• 제31권10호
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• pp.2909-2912
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• 2010

Hydrogenated microcrystalline silicon (${\mu}c$-Si:H) thin film for solar cells is prepared by plasma-enhanced chemical vapor deposition and physical properties of the ${\mu}c$-Si:H p-layer has been investigated. With respect to stable efficiency, this film is expected to surpass the performance of conventional amorphous silicon based solar cells and very soon be a close competitor to other thin film photovoltaic materials. Silicon in various structural forms has a direct effect on the efficiency of solar cell devices with different electron mobility and photon conversion. A Raman microscope is adopted to study the degree of crystallinity of Si film by analyzing the integrated intensity peaks at 480, 510 and $520\;cm^{-1}$, which corresponds to the amorphous phase (a-Si:H), microcrystalline (${\mu}c$-Si:H) and large crystals (c-Si), respectively. The crystal volume fraction is calculated from the ratio of the crystalline and the amorphous phase. The results are compared with high-resolution transmission electron microscopy (HR-TEM) for the determination of crystallinity factor. Optical properties such as refractive index, extinction coefficient, and band gap are studied with reflectance spectra.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1999년도 추계학술발표강연 및 논문개요집
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• pp.75-75
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• 1999

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2003년도 추계학술발표회초록집
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• pp.89-90
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• 2003