• 한국표면공학회지
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• 제22권4호
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• pp.215-220
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• 1989

Silicon Nitride whose thickness is about $100\AA$by the ellipsometer was successfully formed by the Plasma reaction. Nitrogen Plasma was formed by applying the 200KHz, 500Watt power between the two electroes and nitridation of silicon was carried out directly on the top of the silicon wafer. Thus Silicon Nitride formed was oxidized to from oxynitrides and their electrical characterlstice were analyzed by measuring I-V curves and capacitances. Through ESCA depth profiles, the chemical composition changes before and after the oxidation wers analyzed.

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2005년도 전기학술대회논문집
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• pp.1016-1021
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• 2005

A piezoresistive pressure sensor using a silicone rubber membrane has been fabricated on the selectively diffused (100)-oriented n/n+/n silicon substrates by a unique silicon micromachining technique using porous silicon ething. The width, length and thickness of the beam were 120${\mu}m$, 600${\mu}m$ and 7${\mu}m$, respectively and the thickness of the silicone rubber membrane was 40${\mu}m$. By the fusion of silicon beam and silicone rubber membrane, the mechanical strength of the pressure sensor could be highly improved due to smaller shear stress. The effectiveness of the sensor was confirmed through an experiment and FEM simulation in which the pressure sensor was characterized.

• 전기학회논문지
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• 제66권2호
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• pp.354-356
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• 2017

We focused on light management technology in amorphous silicon solar cells to suppress increase in absorber thickness for improving power conversion efficiency (PCE). $MgF_2$ and $TiO_2$ anti-reflection layers were coated on both sides of Asahi VU ($glass/SnO_2:F$) substrates, which contributed to increase in PCE from 9.16% to 9.81% at absorber thickness of only 150 nm. Also, we applied very thin $MgF_2$ as a rear reflector at n-type nanocrystalline silicon oxide/Ag interface to boost photocurrent. By reinforcing rear reflection, we could find the PCE increase from 10.08% up to 10.34% based on thin absorber about 200 nm.

• 한국세라믹학회지
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• 제28권11호
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• pp.859-864
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• 1991

High quality lead titanate thin films were fabricated by spin coating on a silicon substrate. The resulting dried gel layers were uniform in thickness through 2$\times$2 $\textrm{cm}^2$ area, and polycrystalline perovskite structures developed almost crack free with a heat treatment above 50$0^{\circ}C$ in films with thickness above 360 nm. Metastable pyrochlore structures were observed in films with thickness of 160 nm when heat treated at 500 and $600^{\circ}C$, but these structure did not appear in films with thickness of 360 nm. The thickness dependence in crystal structure of films was studied. by varying the substrate condition and analyzing the interface between the film and substrate. In native oxide films on silicon stbstrates, amorphous dried gel layers were heterogeneously nucleated. Metastable cubic pyrochlore structure could be crystallized in amorphous native oxide.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.7-8
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• 2005

The pseudo MOSFET measurement technique has been a simple and rapid method for characterization of SOI wafers without any device fabrication process. We adopted the pseudo MOSFET technique to examine the surface silicon film thickness dependence of electrical properties of SOI wafer. The measurements showed that turn-on voltage increased and electron mobility decreased as the SOI film thickness was reduced in the SOI film thickness of less than 20 nm region.

• 한국산학기술학회논문지
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• 제5권4호
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• pp.367-370
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• 2004

초고속 RF IC의 핵심소자인 SiGe 에피텍시층을 가진 이종양극트란지스터(hetero junction bipolar transistor: HBT)를 0.35㎛급 Si-Ge BiCMOS공정으로 제작하였다. 낮은 VBE영역에서의 current gain의 선형성을 향상시키기 위하여 SiGe에피텍시층의 결함밀도를 감소시킬 수 있는 캐핑실리콘의 두께와 EDR온도의 최적화 공정조건을 알아보았다. 캐핑 실리콘의 두께를 200Å과 300Å으로 나누고 초고속 무선통신에서 요구되는 낮은 노이즈를 위한 EDR(Emitter Drive-in RTA)의 온도와 시간을 900-1000℃, 0-30 sec로 각각 변화시키면서 최적조건을 확인하였다. 실험범위 내에서의 최적공정조건은 300Å의 capping 실리콘과 975℃-30sec의 EDR 조건을 확인하였다.

• Journal of Korean Vacuum Science & Technology
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• 제2권2호
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• pp.122-132
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• 1998

Characteristics of inductively coupled Cl2/O2 and Cl2/N2 plasmas and their effects on the formation of submicron deep trench etching of single crystal silicon have been investigated using Langmuir probe, quadrupole mass spectrometer (QMS), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM), Also, when silicon is etched with oxygen added chlorine plasmas, etch products recombined with oxygen such as SiClxOy emerged and Si-O bondings were found on the etched silicon surface. However, when nitrogen is added to chlorine, no etch products recombined with nitrogen nor Si-N bondings were found on the etched silicon surface. When deep silicon trenches were teached, the characteristics of Cl2/O2 and Cl2/N2 plasmas changed the thickness of the sidewall residue (passivation layer) and the etch profile. Vertical deep submicron trench profiles having the aspect ratio higher than 5 could be obtained by controlling the thickness of the residue formed on the trench sidewall using Cl2(O2/N2) plasmas.

• 한국정보통신학회논문지
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• 제21권8호
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• pp.1465-1470
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• 2017

기존의 MOSFET에서는 반전층보다 항상 실리콘 두께가 크기 때문에 드레인유도 장벽감소가 실리콘 두께에 관계없이 산화막 두께 및 채널길이의 함수로 표현되었다. 그러나 10 nm 이하 저도핑 이중게이트 구조에서는 실리콘 두께 전체가 공핍층이 형성되기 때문에 기존의 SPICE 모델을 사용할 수 없게 되었다. 그러므로 이중게이트 MOSFET에 대한 새로운 SPICE 용 드레인유도 장벽감소 모델을 제시하고자 한다. 이를 분석하기 위하여 전위분포와 WKB 근사를 이용하여 열방사 및 터널링 전류를 구하였다. 결과적으로 드레인유도 장벽감소는 상하단 산화막 두께의 합 그리고 실리콘 두께의 2승에 비례하며 채널길이의 3승에 반비례한다는 것을 알 수 있었다. 특히 SPICE 파라미터인 정적 궤환계수가 1과 2사이에서 사용할 수 있어 합당한 파라미터로써 사용할 수 있었다.

• 한국결정성장학회지
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• 제15권6호
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• pp.260-262
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• 2005

Thickness optimization of heavily doped p-type seeding layer was studied to improve performance of thin film silicon solar cell. We used liquid phase epitaxy (LPE) to grow active layer of $25{\mu}m$ thickness on $p^+$ seeding layer. The cells with $p^+$ seeding layer of $10{\mu}m\;to\;50{\mu}m$ thickness were fabricated. The highest efficiency of a cell is 12.95%, with $V_{oc}=633mV,\;J_{sc}=26.5mA/cm^2$, FF = 77.15%. The $p^+$ seeding layer of the cell is $20{\mu}m$ thick. As thicker seeding layer than $20{\mu}m$, the performance of the cell was degraded. The results demonstrate that the part of the recombination current is due to the heavily doped seeding layer. Thickness of heavily doped p-type seeding layer was optimized to $20{\mu}m$. The performance of solar cell is expected to improve with the incorporation of light trapping as texturing and AR coating.