• Title/Summary/Keyword: Silicon substrate

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The Simulation of Selective Emitter Formation for Crystalline Silicon Solar Cell by Growing Thermal Oxide (Thermal oxidation을 이용한 결정질 실리콘 태양전지의 selective emitter 형성 방법에 대한 simulation)

  • Choe, Yonghyon;Son, Hyukjoo;Lee, Inji;Park, Jeagun;Park, Yonghwan
    • 한국신재생에너지학회:학술대회논문집
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    • 2010.11a
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    • pp.53.1-53.1
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    • 2010
  • 결정질 실리콘 태양전지의 효율을 향상시키기 위하여 수광면에 서로 다른 도핑농도를 가지는 고농도 도핑영역과 저농도 도핑영역으로 이루어진 emitter를 형성하는 것이 요구되며 이를 selective emitter라 칭한다. Selective emitter를 형성하면 고농도 도핑영역에서 금속전극과 저항 접촉이 잘 형성되기 때문에 직렬 저항이 최소화되고 저농도 도핑영역에서는 전하 재결합의 감소로 인하여 태양전지의 변환효율이 상승하는 이점이 있다. Selective emitter의 형성방법은 이미 다양한 방법이 제안되고 있으나, 본 연구에서는 기존에 제시된 방법과는 다르게 열산화 시 dopant redistribution에 의한 Boron depletion 현상을 이용하여 selective emitter를 형성하는 방법을 제안하였고, 이를 Simulation을 통하여 검증하였다. 초기 emitter 확산 후 junction depth는 0.478um, 면저항은 $104.2{\Omega}/sq.$ 이었으며, nitride masking layer 두께는 0.3um로 설정하였다. $1100^{\circ}C$에서 30분간 습식산화 공정을 거친 후 nitride mask가 있는 부분의 junction depth는 1.48um, 면저항은 $89.1{\Omega}/sq$의 값을 보였고, 산화막이 형성된 부분의 junction depth는 1.16um, 면저항은 $261.8{\Omega}/sq$의 값을 보였다. 위 조건의 구조를 가진 태양전지의 변환 효율은 19.28%의 값을 나타내었고 Voc, Jsc 및 fill factor는 각각 645.08mV, $36.26mA/cm^2$, 82.42%의 값을 보였다. 한편 일반적인 구조로 설정한 태양전지의 변환 효율, Voc, Isc 및 fill factor는 각각 18.73%, 644.86mV, $36.26mA/cm^2$, 80.09%의 값을 보였다.

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The optical properties of columnar structure according to the growth angles of ZnO thin fims (성장각도에 따른 주상구조 ZnO 박막의 광학적 특성)

  • Ko, Ki-Han;Seo, Jae-Keun;Kim, Jae-Kwang;Kang, Eun-Kyu;Park, Mun-Gi;Ju, Jin-Young;Shin, Yong-Deok;Choi, Won-Seok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.127-127
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    • 2009
  • The most important part of the fabrication solar cells is the anti-reflection coating when excludes the kinds of silicon substrates (crystalline, polycrystalline, or amorphous), patterns and materials of electrodes. Anti-reflection coatings reduce the reflection of sunlight and at last increase the intensity of radiation to inside of solar cells. So, we can obtain increase of solar cell efficiency about 10% using anti-reflection coating. There are many kinds of anti-reflection film for solar cell, such as SiN, $SiO_2$, a-Si, and so on. And, they have two functions, anti-reflection and passivation. However such materials could not perfectly prevent reflection. So, in this work, we investigated the anti-reflection coating with the columnar structure ZnO thin film. We synthesized columnar structure ZnO film on glass substrates. The ZnO films were synthesized using a RF magnetron sputtering system with a pure (99.95%) ZnO target at room temperature. The anti-reflection coating layer was sputtered by argon and oxygen gases. The angle of target and substrate measures 0, 20, 40, 60 degrees, the working pressure 10 mtorr and the 250 W of RF power during 40 minutes. The confirm the growth mechanism of ZnO on columnar structure, the anti-reflection coating layer was observed by field emission scanning electron microscopy (FE-SEM). The optical trends were observed by UV-vis and Elleso meter.

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(Signal Integrity Verification of a General VLSI Interconnects using Virtual-Straight Line Model) (가상 직선 모델을 사용한 일반적 VLSI 배선의 신호의 무결성 검증)

  • Jin, U-Jin;Eo, Yeong-Seon;Sim, Jong-In
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.39 no.2
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    • pp.146-156
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    • 2002
  • In this paper, a new virtual-straight line parameter determination methodology and fast time domain simulation technique for non-uniform interconnects are presented and verified. Time domain signal response of interconnects circuit considering the characteristic of non-linear transistor is performed by using model order reduction method. Since model order reduction method is peformed by using per unit length parameters, virtual- straight line parameters for non-uniform interconnects are determined. Its method is integrated into Berkeley SPICE and shown that time domain signal responses using proposed method have a good agreement with the results of conventional circuit simulator HSPICE. The proposed method can be efficiently employed in the high-performance VLSI circuit design since it can provide a fast and accurate time domain signal response of complicated multi - layer interconnects.

A Study of Nickel Silicide Formed on SOI Substrate with Different Deposited Ni/Co Thicknesses for Nanoscale CMOSFET (나노급 CMOSFET을 위한 SOI 기판에서의 Ni/Co 증착 두께에 따른 Nickel silicide 특성 분석)

  • Jung, Soon-Yen;Yum, Ju-Ho;Jang, Houng-Kuk;Kim, Sun-Yong;Shin, Chang-Woo;Oh, Soon-Young;Yun, Jang-Gn;Kim, Yong-Jin;Lee, Won-Jae;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.619-622
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    • 2005
  • 본 논문에서는 서로 다른 Si 두께 ($T_{Si}$ = 27, 50 nm) 를 갖는 SOI (Silicon On Insulator) 기판 위에 다양한 두께의 Ni/Co를 순차적으로 증착한 후 Bulk-Si과의 비교를 통해 Silicide의 형성 특성에 대하여 분석하였다. 우선 급속 열처리 (RTP, Rapid Thermal Processing) 를 통하여 Silicide를 형성한 후 측정결과 Si두께에 따라 Silicide의 특성이 달라짐을 확인하였다. 두꺼운 두께의 Si-film을 갖는 SOI 기판을 사용한 경우 증착된 금속의 두께에 따라 Bulk-Si와 비슷한 면저항 특성을 보였으나, 얇은 두께의 Si-film을 갖는 SOI기판을 사용한 경우에는 제한된 Si의 공급으로 인한 Silicide의 비저항 증가로 인하여 증착된 금속의 두께에 따라 면저항이 감소하다가 다시 증가하는 'V' 자형 곡선을 나타내었다.

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Copper Ohmic Contact on n-type SiC Semiconductor (탄화규소 반도체의 구리 오옴성 접촉)

  • 조남인;정경화
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.4
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    • pp.29-33
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    • 2003
  • Material and electrical properties of copper-based ohmic contacts on n-type 4H-SiC were investigated for the effects of the post-annealing and the metal covering conditions. The ohmic contacts were prepared by sequential sputtering of Cu and Si layers on SiC substrate. The post-annealing treatment was performed using RTP (rapid thermal process) in vacuum and reduction ambient. The specific contact resistivity ($p_{c}$), sheet resistance ($R_{s}$), contact resistance ($R_{c}$), transfer length ($L_{T}$), were calculated from resistance (RT) versus contact spacing (d) measurements obtained from TLM (transmission line method) structure. The best result of the specific contact resistivity was obtained for the sample annealed in the reduction ambient as $p_{c}= 1.0 \times 10^{-6}\Omega \textrm{cm}^2$. The material properties of the copper contacts were also examined by using XRD. The results showed that copper silicide was formed on SiC as a result of intermixing Cu and Si layer.

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Characterization of carrier transport and trapping in semiconductor films during plasma processing

  • Nunomura, Shota;Sakata, Isao;Matsubara, Koji
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.391-391
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    • 2016
  • The carrier transport is a key factor that determines the device performances of semiconductor devices such as solar cells and transistors [1]. Particularly, devices composed of in amorphous semiconductors, the transport is often restricted by carrier trapping, associated with various defects. So far, the trapping has been studied for as-grown films at room temperature; however it has not been studied during growth under plasma processing. Here, we demonstrate the detection of trapped carriers in hydrogenated amorphous silicon (a-Si:H) films during plasma processing, and discuss the carrier trapping and defect kinetics. Using an optically pump-probe technique, we detected the trapped carriers (electrons) in an a-Si:H films during growth by a hydrogen diluted silane discharge [2]. A device-grade intrinsic a-Si:H film growing on a glass substrate was illuminated with pump and probe light. The pump induced the photocurrent, whereas the pulsed probe induced an increment in the photocurrent. The photocurrent and its increment were separately measured using a lock-in technique. Because the increment in the photocurrent originates from emission of trapped carriers, and therefore the trapped carrier density was determined from this increment under the assumption of carrier generation and recombination dynamics [2]. We found that the trapped carrier density in device grade intrinsic a-Si:H was the order of 1e17 to 1e18 cm-3. It was highly dependent on the growth conditions, particularly on the growth temperature. At 473K, the trapped carrier density was minimized. Interestingly, the detected trapped carriers were homogeneously distributed in the direction of film growth, and they were decreased once the film growth was terminated by turning off the discharge.

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Effect of a 3C-SiC buffer layer on SAW properties of AlN films (3C-SiC 버퍼층이 AlN 박막형 SAW 특성에 미치는 영향)

  • Hoang, Si-Hong;Chung, Gwiy-Sang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.235-235
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    • 2009
  • This paper describes the influence of a polycrystalline (poly) 3C-SiC buffer layer on the surface acoustic wave (SAW) properties of poly aluminum nitride (AlN) thin films by comparing the center frequency, insertion loss, the electromechanical coupling coefficient ($k^2$), andthetemperaturecoefficientoffrequency(TCF) of an IDT/AlN/3C-SiC structure with those of an IDT/AlN/Si structure, The poly-AlN thin films with an (0002)-preferred orientation were deposited on a silicon (Si) substrate using a pulsed reactive magnetron sputtering system. Results show that the insertion loss (21.92 dB) and TCF (-18 ppm/$^{\circ}C$) of the IDT/AlN/3C-SiC structure were improved by a closely matched coefficient of thermal expansion (CTE) and small lattice mismatch (1 %) between the AlN and 3C-SiC. However, a drawback is that the $k^2(0.79%)$ and SAW velocity(5020m/s) of the AlN/3C-SiC SAW device were reduced by appearing in some non-(0002)AlN planes such as the (10 $\bar{1}$ 2) and (10 $\bar{1}$ 3) AlN planes in the AlN/SiC film. Although disadvantages were shown to exist, the use of the AlN/3C-SiC structure for SAW applications at high temperatures is possible. The characteristics of the AlN thin films were also evaluated using FT-IR spectra, XRD, and AFM images.

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Characteristics of the NO/$N_2O$ Nitrided Oxide and Reoxidized Nitrided Oxide for NVSM (비휘발성 기억소자를 위한 NO/$N_2O$ 질화산화막과 재산화 질화산화막의 특성에 관한 연구)

  • 이상은;서춘원;서광열
    • Journal of the Korean Vacuum Society
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    • v.10 no.3
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    • pp.328-334
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    • 2001
  • The characteristics of $NO/N_2O$ nitrided oxide and reoxidized nitrided oxide being studied as super thin gate oxide and gate dielectric layers of nonvolatile semiconductor memory(NVSM) was investigated by dynamic secondary ion mass spectrometry(D-SMS), time-of-flight secondary ion mass spectrometry(ToF-SIMS), and x-ray photoelectron spectroscopy (XPS). The specimen was annealed in $NO/N_2O$ ambient after initial oxide process. The result of D-SIMS exhibits that the center of nitrogen exists at the initial oxide interface and the distribution of nitrogen is wider in the annealing process with $N_2O$ than with NO annealing process. For investigating the condition of nitrogen that exists within the nitrided oxide, ToF-SIMS and XPS analysis were carried out. It was shown that the center of nitrogen investigated by D-SIMS was expected the SiON chemical bonds. The nitrogen near the newly formed reoxide/silicon substrate interface was appeared as $Si_2NO$ chemical bonds, and it is agreed with the distribution of SiN and $Si_2NO$ species by ToF-SIMS.

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The defect nature and electrical properties of the electron irradiated $p^+-n^-$ junction diode (전자 조사된 $p^+-n^-$ 접합 다이오드의 결함 특성과 전기적 성질)

  • 엄태종;강승모;김현우;조중열;김계령;이종무
    • Journal of the Korean Vacuum Society
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    • v.13 no.1
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    • pp.14-21
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    • 2004
  • It is essential to increase the switching speed of power devices to reduce the energy loss because high frequency is commonly used in power device operation these days. In this work electron irradiation has been conducted to reduce the lifetime of minority carriers and thereby to increase the switching speed of a$p^+- n^-$ junction diode. Effects of electron irradiation on the electrical properties of the diode are reported The switching speed is effectively increased. Also the junction leakages and the forward voltage drop which are anticipated to increase are found to be negligible in the $p^+- n^-$ junction diodes irradiated with the optimum energy and dose. The analysis results of DLTS and C-V profiling indicate that the defects induced by electron irradiation in the silicon substrate are donor-like ones which have the energy levels of 0.284 eV and 0.483 eV. Considering all the experimental results in this study, it might be concluded that electron irradiation is a very useful technique in improving the switching speed and thereby reducing the energy loss of $p^+- n^-$ junction diode power devices.

A High Tunable Capacitor Embedding Its Electrodes in Tunable Thin Film Dielectrics (가변형 박막 유전체에 전극을 임베디드 시킨 고가 변형 커패시터)

  • Lee Young-Chul;Hong Young-Pyo;Ko Kyung-Hyun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.9 s.112
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    • pp.860-865
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    • 2006
  • In this paper, a novel tunable inter-digital capacitor using dielectric tunable $Bi_2O_3-ZnO-Nb_2O_5(BZN)$ pyrochlore thin films is proposed. In order to improve the tunability and reduce DC bias voltage using the fringing electric field, the electrodes of the inter-digital capacitor are embedded in the thin film. Designed results using a 2.5 D simulator show that the tunability of the proposed inter-digital capacitor improves by 10 %, compared to the conventional inter-digital capacitor. The proposed IDC, which is based on the simulation results, was fabricated, using the BZN thin film deposited by a reactive RF magnetron sputtering on the on the silicon substrate. The fabricated inter-digital capacitor shows the maximum tunability of 50 % at 5.8 GHz and 18 V DC applied.