• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

• Journal of IKEEE
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• v.19 no.2
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• pp.265-270
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• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.45-53
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• 2013

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

• Progress in Superconductivity and Cryogenics
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• v.15 no.4
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• pp.30-33
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• 2013

The studies of superconducting fault current limiter (SFCL) for reduction of the fault current are actively underway in the worldwide. In this paper, we analyzed the characteristics of a new type SFCL using the conventional transformer and superconducting elements combined mutually. The secondary and third windings of this SFCL were connected the load and the superconducting element, respectively. The electric power was provided to load connected to secondary windings of the transformer in normal state of power system. On the other hand, when the fault occurred in power system, the fault current was limited by closing the line of third winding of the transformer. At this time, the ripple phenomenon of the fault was minimized by opening the fault line in secondary winding of a transformer in power system. The sensing of the fault state was performed by the CT(current transformer) and then turn-on and turn-off switching behavior of the SFCL was performed by the SCR(silicon-controlled rectifier). As a result, the proposed SFCL limited the fault current within a half-cycle efficiently. We confirmed that the fault current limitation rate was changed according to the winding ratio of a transformer.

• KIEE International Transactions on Electrophysics and Applications
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• v.2C no.6
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• pp.304-308
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• 2002

We demonstrate a simple pulsed $CO_2$ laser with millisecond long pulse duration in a tube at a low pressure of less than 30 Torr. The novel power supply for our laser system switches the voltage of the AC power line (60Hz) directly. The power supply doesn't need elements such as a rectifier bridge, energy-storage capacitors, or a current-limiting resistor in the discharge circuit. To control the laser output power, the pulse repetition rate is adjusted up to 60Hz and the firing angle of SCR(Silicon Controlled Rectifier) gate is varied from 30。 to 150。. A ZCS (Zero Crossing Switch) circuit and a PIC one-chip microprocessor are used to control precisely the gate signal of the SCR. The maximum laser output of 35 W is obtained at a total pressure of 18 Torr, a pulse repetition rate of 60 Hz, and a SCR gate firing angle of 90。 . In addition, the resulting laser pulse width is approximately 3㎳(FWHM). This is a relatively long pulse width, compared with other repetitively pulsed $CO_2$ lasers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.601-607
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• 2015

A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1088-1090
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• 2001

In general, Power SCR(Silicon Controlled Rectifier) is most widely used in Power Plant as well as Industrial field. It has been controlled and operated according to its own control method. Especially, in case of Power plant, it plays a major role in AVR(Automatic Voltage Regulator) or electro chlorination control circuits. Generally, they used in Analog control system at above field. But each SCR current value is different because of load unbalance or switching characteristic variations, it may cause power plant unit trip or system disorder according to SCR element burn out or bad operating condition. Therefore, in this paper a development of 3 phase current balance control unit is described, it gets over the past analog control system limit, uses DSP(Digital signal processor) had high speed response, controls SCR gate firing angle for 3 phase current balance.

• Journal of IKEEE
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• v.21 no.3
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• pp.234-239
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• 2017

In this paper, we propose an ESD (Electrostatic Discharge) protection circuit based on a new structure of SCR (Silicon Controlled Rectifier) embedded with PMOS structure. The proposed ESD protection circuit has a built-in PMOS structure and has a latch-up immunity characteristic and an improved tolerance characteristic. To verify the characteristics of the proposed ESD protection circuit and to analyze its operating characteristics, we compared and analyzed the characteristics of the existing ESD protection circuit using TCAD simulation. Simulation results show that the proposed protection ESD protection circuit has superior latch-up immunity characteristics like the existing SCR-based ESD protection device HHVSCR (High Holding Voltage SCR). Also, according to the results of the HBM (Human Body Model) maximum temperature test, the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower than the existing HHVSCR 373K. In addition, the proposed ESD protection circuit with improved electrical characteristics is designed by applying N-STACK technology. As a result of the simulation, the proposed ESD protection circuit has a holding voltage characteristic of 2.5V in a single structure, and the holding voltage increased to 2-STACK 4.2V, 3-STACK 6.3V, 4-STACK 9.1V.