• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1919-1928
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• 1999

There are no standard language for the specification of speed-independent circuits because existing specification methods are designed appropriately to each synthesis methodology. This paper suggests a method of using VHDL, a standard hardware description language, for the specification and synthesis of speed-independent circuits. Because VHDL is a multi-purpose language, we define a subset of VHDL which can be used for the synthesis. We transform the VHDL description into a signal transition graph and then synthesize speed-independent circuits by using a previous synthesis algorithm which uses a signal transition graph as the specification method. We suggest a systematic transformation method which transforms each VHDL statement into a partial signal transition graph and then merges them into a signal transition graph. This work is a step towards to the development of an integrated framework in which we can utilizes the existing CAD tools based on VHDL. Also, this work will enable a easier migration of the current circuit designers into asynchronous circuit design.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.216-226
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• 2000

This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a deterministic signal transition graph specification with timing constraints. First, a timing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. Then, a hazard-free implementation under the timing constraints is synthesized by constructing a precedence graph and finding paths in the graph. The major result of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in synthesis time, and generates circuits that have nearly the same area as compared to previous methods.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.137-140
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• 2000

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.195-204
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• 1996

We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.43-47
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• 1984

This paper describes the mean time delay and its variance before transition from search to lock mode by means of signal flow graph and its transfer function. A relation between hit probability and search stage number is presented with the comparison of the open loop and closed loop. From these results optimum transition probability which we must hold can be obtained.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.47-55
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• 1999

In this paper, a new function hazard elimination algorithm is proposed for asynchronous circuit synthesis. In previous approach, function hazard is eliminated by using state graph which is obtained from the state assignment on STG(signal transition graph) representing transition relationship among signals. These algorithms can use conventional hazard removal and synthesis method applied in synchronous system, but it has much computational complexity and takes much time to handle the state graph. Although some hazard elimination algorithm from STG were proposed, it could not reduce the area overhead due to the addition of new signals. The proposed algorithm eliminate function hazard directly on STG and also control the number of minterms and product-term of added signal in order to minimize the area overhead. Experimental results on benchmark data shows that overall circuit area after hazard elimination is decreased about 15% on the average than that of previous method.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.351-362
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• 2002

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

• Proceedings of the IEEK Conference
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• summer
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• pp.259-262
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• 2004

In most of the character recognition systems, the method of template matching or statistical method using hidden Markov model is used to extract and recognize feature shapes. In this paper, we used modified chain-code which has 8-directions but 4-codes, and made the chain-code of hand-written character, after that, converted it into transition chain-code by applying to HMM(Hidden Markov Model). The transition chain code by HMM is analyzed as signal flow graph by Mason's theory which is generally used to calculate forward gain at automatic control system. If the specific forward gain and feedback gain is properly set, the forward gain of transition chain-code using Mason's theory can be distinguished depending on each object for recognition. This data of the gain is reorganized as tree structure, hence making it possible to distinguish different hand-written characters. With this method, $91\%$ recognition rate was acquired.

• 전기의세계
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• v.21 no.2
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• pp.9-19
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• 1972

The transient characteristics of separately excited d-c motor driven by thyristor d-c chopper is studied in this paper. The armature controlled system is applied. As a result of theoretrical analysis the following conculsions were drawn: (1) For the transient analysis, it is recognized that the state transition analysis is a more general method and powerful tool than the state equation method or signal flow graph method, although it includes iterative matrix calculations. And the system is dealt with a finite width sampled-data system in the state transition analysis. (2) The transient characteristics of the motor angular velocity and its torque to the sampling duration variation are compared with those due to the amplitude variation of d-c chopper voltage as follows. The attenuation rate of the transient characteristics is equal in both cases, but the initial value of the transient characteristics in former case is greater than in latter case. (3) The roots of characteristics equation of the system lie inside the unit circle of the Z-plane. Therefor the system is stable. Further it is found that as the sampling duration is decreased the relative stability is lessened.