• 제목/요약/키워드: SiC film

검색결과 2,120건 처리시간 0.026초

스크린 프린팅법으로 제조된 PAN-PZT 후막의 특성 (Charicteristics of PAN-PZT Thick Films on Si-Substrate by Screen Printing)

  • 김상종;최지원;김현재;성만영;윤석진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.139-142
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    • 2002
  • Characteristics of piezoelectric thick films prepared by screen printing were investigated. The piezoelectric thick films were fabricated using Pb(Al,Nb)O$_3$-Pb(Zr,Ti)O$_3$ system on Si-substrate. The fabricated thick films were burned out at 400$^{\circ}C$ and sintered at 850∼1000$^{\circ}C$ using rapid thermal annealing(RTA) precess. The thickness of piezoelectric thick films were 10$\mu\textrm{m}$. PAN-PZT thick film on Ag-Pd/SiO$_2$/Si prepared at 900$^{\circ}C$/1300sec had remanent polarization of 19.70 ${\mu}$C/$\textrm{cm}^2$.

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SiO2 보호막 증착에 따른 p-GaN의 후열처리 효과 연구

  • 박진영;지택수;이진홍;안수창
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2013년도 춘계학술대회
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    • pp.772-775
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    • 2013
  • 사파이어 위에 MOCVD로 성장한 p-GaN 위에 PECVD로 $SiO_2$ $2500{\AA}$을 증착하여 열처리실험을 진행하였다. 열처리 후 $SiO_2$ 보호막을 식각하여, 정공 농도를 측정하고, 이를 열처리 전의 데이터 값과 비교, 분석하였다. 또한, 분위기가스인 $N_2$$O_2$의 비율, 급속 열처리 온도 ($650^{\circ}C$$750^{\circ}C$) 및 시간(1분~15분)에 따른 정공의 이동도와 농도의 변화를 측정하였으며, 상온 및 저온 PL 측정을 통하여 후열처리에 따른 시료의 광학적, 구조적 성질을 조사하였다.

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N-type 결정질 실리콘 태양전지 응용을 위한 Al2O3 박막의 패시베이션 특성 연구 (Passivation property of Al2O3 thin film for the application of n-type crystalline Si solar cells)

  • 정명일;최철종
    • 한국결정성장학회지
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    • 제24권3호
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    • pp.106-110
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    • 2014
  • Atomic layer deposition(ALD)을 이용하여 $Al_2O_3$ 박막을 형성하고 이에 대한 패시베이션 특성에 대한 연구를 수행하였다. ALD로 증착된 $Al_2O_3$ 박막은 $400^{\circ}C$ 5분간 후속 열처리 공정 후에도 $Al_2O_3$ - 실리콘 계면 반응 없이 비정질 상태를 유지할 만큼 구조적으로 안정한 특성을 나타내었다. 후속 열처리 후 $Al_2O_3$ 박막의 패시베이션 특성이 향상되었으며, 이는 field effective 패시베이션과 화학적 패시베이션 효과가 동시에 상승에 기인하는 것으로 판단된다. $Al_2O_3$ 박막의 음고정 전하를 정량적으로 평가하기 위해서 후속 열처리 공정을 거친 $Al_2O_3$ 박막을 이용하여 metal-oxide-semiconductor(MOS) 소자를 제작하고 capacitance-voltage(C-V) 분석을 수행하였다. C-V 결과로부터 추출된 flatband voltage($V_{FB}$)와 equivalent oxide thickness(EOT)의 관계식을 통하여 $Al_2O_3$ 박막의 고정음전하는 $2.5{\times}10^{12}cm^{-2}$로 계산되었으며, 이는 본 연구에서 제시된 $Al_2O_3$ 박막 공정이 N-type 실리콘 태양전지의 패시베이션 공정에 응용 가능하다는 것을 의미한다.

열처리온도에 따른 $SnO_2$/Si 이종접합 태양전지의 전기적 특성 (Electrical characteristics of Sn $O_{2}$Si heterojunction solar cells depending on annealing temperature)

  • 이재형;박용관
    • E2M - 전기 전자와 첨단 소재
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    • 제7권6호
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    • pp.481-489
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    • 1994
  • The $SnO_2$/(n)Si solar cell was fabricated by electron beam evaporation method, and their properties were investigated. In proportion to increase of substrate and annealing temperature, the conductivity of $SnO_2$ thin film was increased, but its optical transmission decreases because of increasing optical absorption of free electrons in the thin film. $SnO_2$/Si Solar cell characteristics were improved by annealing, but the solar cells was deteriorated by heat treatment above 500[.deg. C]. The optimal outputs of $SnO_2$/Si solar cell through above investigations were $V_{\var}$:350[mV], $J_{sc}$ ;16.53[mA/c $m^{2}$], FF;0.41, .eta.=4.74[%]

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저온 변조 성장 기법을 이용하여 Sb가 ${\delta}$ 도핑된 다층 구조의 Si 분자선 박막 성장과 특성 분석 (Molecular beam epitaxial growth and characterization of Sb .delta.-doped Si layers using substrate temperature modulation technique)

  • Le, Chan ho
    • 전자공학회논문지A
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    • 제32A권12호
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    • pp.142-148
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    • 1995
  • Sb ${\delta}$-doped Si layers were grown by Si MBE (Molecular Beam Epitaxy) system using substrate temperature modulation technique. The Si substrate temperatures were modulated between 350$^{\circ}C$ and 600$^{\circ}C$. The doping profile was as narrow as 41$\AA$ and the doping concentration of up to 3.5${\times}10^{20}cm^{3}$ was obtained. The film quality was as good as bulk material as verified by RHEED (Reflected High Energy Electron Diffraction), SRP (Spreading Resistance Profiling) and Hall measurement. Since the film quality is not degraded after the growth a Sb ${\delta}$-doped Si layer, the ${\delta}$-doped layers can be repeated as many times as we want. The doping technique is useful for many Si devices including small scale devices and those which utilize quantum mechanical effects.

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WSi2 word-line 및 bit-line용 spacer-Si3N4 박막의 증착 (Deposition of Spacer-Si3N4 Thin Film for WSi2 Word-Line and Bit-Line)

  • 안승준;김대욱;김종해;안성준;김영정;김호섭
    • 한국재료학회지
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    • 제14권6호
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    • pp.402-406
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    • 2004
  • $WSi_2$, $TiSi_2$, $CoSi_2$, and $TaSi_2$ are general silicides used today in semiconductor devices. $WSi_2$ thin films have been proposed, studied and used recently in CMOS technology extensively to reduce sheet resistance of polysilicon and $n^{+}$ region. However, there are several serious problems encountered because $WSi_2$ is oxidized and forms a native oxide layer at the interface between $WSi_2$ and $Si_3$$N_4$. In this study, we have introduced 20 $slm-N_2$ gas from top to bottom of the furnace in order to control native oxide films between $WSi_2$ and $Si_3$$N_4$ film. In resulting SEM photographs, we have observed that the native oxide films at the surface of $WSi_2$ film are removed using the long injector system.

고온 전자빔 증착에 의한 Ethylene Terephthalate상의 SiOx 박막의 특성 평가 (Characteristics of Defects in SiOx Thin films on Ethylene Terephthalate by High-temperature E-beam Deposition)

  • 한진우;김영환;김종환;서대식;문대규
    • 한국전기전자재료학회논문지
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    • 제19권1호
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    • pp.71-74
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    • 2006
  • In this paper, we investigated the characterization of silicon oxide(SiOx) thin film on Ethylene Terephthalate(PET) substrates by e-beam deposition for transparent barrier application. The temperature of chamber increases from $30^{\circ}C$ to $110^{\circ}C$, the roughness increase while the Water vapor transmission rate (WVTR) decreases. Under these conditions, the WVTR for PET can be reduced from a level of $0.57 g/m^2/day$ (bare subtrate) to $0.05 g/m^2/day$ after application of a 200-nm-thick $SiO_2$ coating at 110 C. A more efficient way to improve permeation of PET was carried out by using a double side coating of a 5-${\mu}m$-thick parylene film. It was found that the WVTR can be reduced to a level of $-0.2 g/m^2/day$. The double side parylene coating on PET could contribute to the lower stress of oxide film, which greatly improves the WVTR data. These results indicates that the $SiO_2$ /Parylene/PET barrier coatings have high potential for flexible organic light-emitting diode(OLED) applications.

반도체 소자의 표면보호용 PSG/SiN 절연막의 스트레스 거동 (Stress Behavior of PSG/SiN Film for Passivation in Semiconductor Memory Device)

  • 김영욱;신홍재;하정민;최수한;이종길
    • 한국재료학회지
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    • 제1권1호
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    • pp.46-53
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    • 1991
  • 반도체 공정의 최종 보호막으로 주로 사용되는 PSG (Phosphosilicate class), USG (Undoped silicate glass) 및 SiN 막을 CVD 방식으로 deposition 하여 각 막의 스트레스를 막 두께 또는 대기중 방치시간의 함수로 조사하고 Al 배선의 stress-migration 관점에서 평가했다. 그 결과 PSG 막과 USG 막은 tensile stress를 나타내고 두께증가에 따라 스트레스가 증가하였고, SiN 막은 두께에 관계없이 일정한 compressive stress를 나타내었다. PSG 막은 현저한 스트레스 경시변화를 보여 대기중에 방치시 2일이내로 tensile stress가 compressive stress로 변화되었다. 그 주 원인은 PSG 막의 수분 흡수 때문인것이 FTIR 분석으로 밝혀졌고, $300^{\circ}C$에서 20분간 anneal 처리로 $2.5{\times}{10^9}\;dyne/cm^2$의 스트레스 회복이 가능하였다. PSG 막이 포함된 복합막의 경우, 복합막 stress는 PSG 막의 방치시간에 따라 변한다. 즉, 복합막의 스트레스는 복합막을 구성하고 있는 막들의 두께의 함수이다. 또 SiN 막의 강한 압축응력을 완화시켜주는 PSG, USG 막의 스트레스가 큰 인장응력을 나타낼수록 Al 배선의 stress-migration 에 대한 저항은 커진다.

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Growth of oriented $LaF_{3}$ thin films on Si (100) substrates by the pulsed laser deposition method

  • Yokotani, Atsushi;Ito, Tomomi;Sato, Akiko;Kurosawa, Kou
    • 한국결정성장학회지
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    • 제13권4호
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    • pp.157-164
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    • 2003
  • $LaF_{3}$ thin films have been fabricated on Si (100) substrates under the highest possible vacuum condition by pulsed laser deposition (PLD) method. The temperature of the sbustrate varied from $20^{\circ}C$ to $800^{\circ}C$. The films deposited at the higher temperature indicated the sharper peaks in the X-ray diffraction measurement. A highly oriented film was successfully obtained at a substrate temperature of $800^{\circ}C$. The surface observation by the AFM revealed that the many hexagonal structures constructed the film. The XPS analysis revealed that the lacking of F in the film deposited at $600^{\circ}C$ were much more than that in film at $^20{\circ}C$. Adding the adequate amount of $CF_{4}$ gas in the growth chamber can compensate this lacking of F.

The Effects of Nanocrystalline Silicon Thin Film Thickness on Top Gate Nanocrystalline Silicon Thin Film Transistor Fabricated at 180℃

  • Kang, Dong-Won;Park, Joong-Hyun;Han, Sang-Myeon;Han, Min-Koo
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제8권2호
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    • pp.111-114
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    • 2008
  • We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at $180^{\circ}C$. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 nm to 200 nm, the grain size was increased from 20 nm to 40 nm. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 nm are 26, 77 and $119\;cm^2/Vsec$, respectively. The leakage current, however, is increased from $7.2{\times}10^{-10}$ to $1.9{\times}10^{-8}\;A$ at $V_{GS}=-4.4\;V$ when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.