• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• Transactions on Electrical and Electronic Materials
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• 제18권4호
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• pp.199-202
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• 2017

Silicon carbide (SiC) is being spotlighted as a next-generation power semiconductor material owing to the characteristic limitations of the existing silicon materials. SiC has a wider band gap, higher breakdown voltage, higher thermal conductivity, and higher saturation electron mobility than those of Si. When using this material to implement Schottky barrier diode (SBD) devices, SBD-state operation loss and switching loss can be greatly reduced as compared to that of traditional Si. However, actual SiC SBDs exhibit a lower dielectric breakdown voltage than the theoretical breakdown voltage that causes the electric field concentration, a phenomenon that occurs on the edge of the contact surface as in conventional power semiconductor devices. Therefore in order to obtain a high breakdown voltage, it is necessary to distribute the electric field concentration using the edge termination structure. In this paper, we designed an edge termination structure using a field plate structure through oxide etch angle control, and optimized the structure to obtain a high breakdown voltage. We designed the edge termination structure for a 650 V breakdown voltage using Sentaurus Workbench provided by IDEC. We conducted field plate experiments. under the following conditions: $15^{\circ}$, $30^{\circ}$, $45^{\circ}$, $60^{\circ}$, and $75^{\circ}$. The experimental results indicated that the oxide etch angle was $45^{\circ}$ when the breakdown voltage characteristics of the SiC SBD were optimized and a breakdown voltage of 681 V was obtained.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.131-131
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• 2008

Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used a Monte-Carlo method. We studied the effect of channeling by Al implantation simulation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the Al distribution in 4H-SiC through the variation of the implantation energies and the corresponding ratio of the doses. The implantation energies controlled 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2\times10^{14}$ to $1\times10^{15}cm^{-2}$. In the simulation results, the Al ion distribution was deeper as increasing implantation energy and the doping level increased as increasing implantation doses. After the post-implantation annealing, the electrical properties of Al-implanted p-n junction diode were investigated by SILV ACO ATLAS numerical simulator.

• 한국진공학회지
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• 제20권1호
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• pp.50-56
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• 2011

본 논문에서는 버퍼막 두께 및 열처리 온도에 따른 ZnO/b-ZnO/p-Si(111) 기반 이종접합 다이오드 전류 특성에 대한 연구가 진행되었고, b-ZnO (ZnO buffer layer) 버퍼막 두께 및 열처리 온도에 따른 p-Si(111) 기판 위에 증착시킨 ZnO 박막의 구조적, 전기적 특성 또한 연구되었다. X-ray diffraction (XRD) 방법을 이용하여 ZnO 박막의 구조적 특성을 측정하였고, semiconductor parameter analyzer를 이용하여 ZnO/b-ZnO/p-Si(111) 이종접합 다이오드의 I-V 특성을 평가하였다. XRD 분석 결과 버퍼막 열처리 온도 $700^{\circ}C$, 버퍼막 두께 70 nm에서 ZnO 박막은 우세한 (002) 방향의 c-축 배향성을 갖는 육방정계(hexagonal wurtize) 결정 구조를 나타내었다. 전기적 특성인 운반자 농도, 비저항 값의 경우에는 버퍼막 열처리 온도 $700^{\circ}C$, 버퍼막 두께 50 nm에서 우수한 전기적 특성(비저항: $2.58{\times}10^{-4}[{\Omega}-cm]$, 운반자 농도: $1.16{\times}10^{20}[cm^{-3}]$)을 보였다. 또한 ZnO/b-ZnO/p-Si(111) 이종접합 다이오드의 전류 특성은 버퍼막 열처리 온도 $700^{\circ}C$에서 버퍼막 두께가 증가할수록 전류 특성이 향상되는 경향을 보였다.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.387-392
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• 2018

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.697-705
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• 2014

A single chip Programmable AC to DC Power Converter, consisting of wide band gap SiC MOSFET and SiC diodes, has been proposed which converts high frequency ac voltage to a conditioned dc output voltage at user defined given power level. The converter has high conversion efficiency because of negligible reverse recovery current in SiC diode and SiC MOSFET. High frequency operation reduces the need of bigger size inductor. Lead inductors are enough to maintain current continuity. A complete electrical analysis, die area estimation and thermal analysis of the converter has been presented. It has been found that settling time and peak overshoot voltage across the device has reduced significantly when SiC devices are used with respect to Si devices. Reduction in peak overshoot also increases the converter efficiency. The total package substrate dimension of the converter circuit is only $5mm{\times}5mm$. Thermal analysis performed in the paper shows that these devices would be very useful for use as miniaturized power converters for load currents of up to 5-7 amp, keeping the package thermal conductivity limitation in mind. The converter is ideal for voltage requirements for sub-5 V level power supplies for high temperatures and space electronics systems.

• 전자공학회논문지
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• 제53권7호
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• pp.11-16
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• 2016

탄화규소(Silicon Carbide)는 와이드 밴드 갭 물질로써 실리콘(Si)에 비해 고전력, 고주파, 고온 소자용 반도체 물질로서 각광받고 있다. 탄화규소를 이용하여 만든 반도체 소자 중 특히 쇼트키 배리어 다이오드는 현재 가장 많이 사용되는 전력반도체 소자로써 스위칭 속도가 매우 빠르고 낮은 온저항 특성을 가지는 소자이다. 하지만 컨텍 엣지에서의 전계집중으로 인해 항복전압이 낮아지는 단점이 있다. 이를 해결하기 위해 다양한 엣지 터미네이션 기술이 제안되고 있는데, 본 논문에서는 최적의 항복전압을 갖기 위한 이중 필드 플레이트(Double Field Plate) 소자 구조를 제안하였다. 측정결과 제작한 소자는 온저항을 유지한 채 38% 향상된 항복전압을 나타내었다. 제안한 소자 특성 검증을 위해 소자를 설계 및 제작한 후 전기적 특성을 측정하였으며, 이중 필드 플레이트 구조는 길이와 두께가 서로 다른 필드 플레이트를 겹쳐 올림으로써 구현하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1999년도 춘계학술발표강연 및 눈문개요집
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• pp.40-40
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• 1999

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.587-592
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• 2010

We have fabricated schottky barrier diode (SBDs) using polar (c-plane) and non polar (a-, m-plane) n-type 6H-SiC wafers. Ni/SiC ohmic contact was accomplished on the backside of the SiC wafers by thermal evaporation and annealed for 20minutes at $950^{\circ}C$ in mixture gas ($N_2$ 90% + $H_2$ balanced). The specific contact resistance was $3.6{\times}10^{-4}{\Omega}cm^2$ after annealing at $950^{\circ}C$. The XRD results of the alloyed contact layer show that formation of $NiSi_2$ layer might be responsible for the ohmic contact. The active rectifying electrode was formed by the same thermal evaporation of Ni thin film on topside of the SiC wafers and annealed for 5 minutes at $500^{\circ}C$ in mixture gas ($N_2$ 90% + $H_2$ balanced). The electrical properties of SBDs have been characterized by means of I-V and C-V curves. The forward voltage drop is about 0.95 V, 0.8 V and 0.8 V for c-, a- and m-plane SiC SBDs respectively. The ideality factor (${\eta}$) of all SBDs have been calculated from log(I)-V plot. The values of ideality factor were 1.46, 1.46 and 1.61 for c-, a- and m-plane SiC SBDs, respectively. The schottky barrier height (SBH) of all SBDs have been calculated from C-V curve. The values of SBH were 1.37 eV, 1.09 eV and 1.02 eV for c-, a- and m-plane SiC SBDs, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 C
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• pp.1555-1557
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• 2004

The Pt-doped $SnO_2$ thin film for CO sensor applications obtained by RF sputtering from a target of the same compound in an Ar-$O_2$ atmosphere. Pt-SnO2-SiC Schottky diode detection of CO gas Cause the remarkable change in electrical resistivity of the semiconductor. the good gas sensitivity is shown when annealing condition is 600$^{\circ}C$, 1hr in RTP and detected temperature is 350$^{\circ}C$.