• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.129-129
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• 2003

최근에 능동 영역 액정 표시 소자(Active Matrix Liquid Crystal Display, AMLCD)에서 고해상도와 빠른 응답속도를 요구하게 되면서부터 다결정 실리콘(poly-Si) 박막 트랜지스터(Thin Film Transistor, TFT)가 쓰이게 되었다. 그리고 일반적으로 디스플레이의 기판을 상대적으로 저가의 유리를 사용하기 때문에 저온 공정이 필수적이다. 따라서 새로운 저온 결정화 방법과 부가적으로 최근 디스플레이 개발 동향 중 하나인 대화면에 적용 가능한 공정인 금속유도 결정화 (Silicide Mediated Crystallization, SMC)가 연구되고 있다. 이 소자는 top-gated coplanar구조로 설계되었다. (그림 1)(100) 실리콘 웨이퍼위에 3000$\AA$의 열산화막을 올리고, LPCVD로 55$0^{\circ}C$에서 비정질 실리콘(a-Si:H) 박막을 550$\AA$ 증착 시켰다. 그리고 시편은 SMC 방법으로 결정화 시켜 TEM(Transmission Electron Microscopy)으로 SMC 다결정 실리콘을 분석하였다. 그 위에 TFT의 게이트 산화막을 열산화막 만큼 우수한 TEOS(Tetraethoxysilane)소스로 사용하여 실리콘 산화막을 1000$\AA$ 형성하였고 게이트는 3000$\AA$ 두께로 몰리브덴을 스퍼터링을 통하여 형성하였다. 이 다결정 실리콘은 3$\times$10^15 cm^-2의 보론(B)을 도핑시켰다. 채널, 소스, 드래인을 정의하기 위해 플라즈마 식각이 이루어 졌으며, 실리콘 산화막과 실리콘 질화막으로 passivation하고, 알루미늄으로 전극을 형성하였다 그리고 마지막에 TFT의 출력특성과 전이특성을 측정함으로써 threshold voltage, the subthreshold slope 와 the field effect mobility를 계산하였다.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1646-1648
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• 2000

This paper investigated structural and electrical properties of $Y_{2}O_3$ as a buffer layer of sin91r transistor FRAM (ferroelectric RAM). $Y_{2}O_3$ buffer layers were deposited at a low substrate temperature below 400$^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post- annealing temperature, and suppression of interfacial $SiO_2$ layer generation. for a well-fabricated sample, we achieved that leakage current density ($J_{leak}$) in the order of $10^{-7}A/cm2$, breakdown electric field ($E_{br}$) about 2 MV/cm for $Y_{2}O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_{2}O_3$/Si as low as $8.72{\times}10^{10}cm^{-2}eV^{-1}$. The low interface states were obtained from very low lattice mismatch less than 1.75%.

• JOURNAL OF ELECTRICAL WORLD
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• s.297
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• pp.66-72
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• 2001

1957년에 사이리스터가 발표된 이래 파워반도체디바이스(이하 ''파워디바이스''라 한다)의 발전과 더불어 이것을 사용하여 전력변환$\cdot$제어와 이를 응용한 파워일렉트로닉스 산업도 현저한 발전을 이루어 왔다. 21세기를 맞이하여 지구의 유한성을 강하게 인식하고 자원과 에너지를 고도이용하는 순환형 사회에로의 전환을 도모하는 기술혁신과 IT(정보기술)를 구사한 기술보급의 움직임이 활발해지고, 파워일렉트로닉스와 그 키파트인 파워디바이스가 수행하여야 할 역할은 점점 더 중요해지고 있다. 이와 같은 배경 하에서 파워디바이스는 인버터제어를 주목적으로 사이리스터, GTO(Gate Turn-off Thyristor), 바이폴라트랜지스터, MOSFET(Metal Oxide Silicon Field Effect Transistor)에서 IGBT(Insulated Gate Bipolar Transistor)에로 진전되고, 그 응용분야도 가전제품에서 OA, 산업, 의료, 전기자동차, 전철, 전력에 이르는 폭넓은 분야로 확대되었다. 현재 파워디바이스를 취급하는 전력의 범위는 수W의 스위칭 전원에서 GW급의 직류송전까지 9단위까지에 이르러 광범위한 전력 제어가 가능하게 되었다. 한편 응용의 중심이 되는 IGBT는, 고속화와 저손실화 및 파괴 내량의 향상을 지향한 개량을 거듭하여 제5세대제품이 나타나기 시작하였다. 또한 IGBT에 구동$\cdot$보호$\cdot$진단 회로 등을 넣어 모듈화한 IPM(Intelligent Power Module)이 그 편리성과 소형화를 특징으로 파워디바이스의 주역의 자리에 정착하였다. 가전$\cdot$산업$\cdot$자동차$\cdot$전철의 각 분야에서는 시장 니즈에 최적 설계된 IPM이 개발되게 되어 보다 더한 시장확대가 기대되고 있다. 또한 종래의 Si(실리콘)에 대신하는 반도체 재료로서 SiC(실리콘 카바이드 : 탄화규소)에 대한 기대가 크고 MOSFET나 SBD 등의 파워디바이스의 조기실용화에의 대처노력도 주목할 만하다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.623-627
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• 1999

We report a new in-situ fluorine passivation method without in implantation by employing excimer laser annealing of $SiO_{x}F_{y}$/a-Si structure and its effects on p-channel poly-Si TFTs. The proposed method doesn't require any additional annealing step and is a low temperature process because fluorine passivation is simultaneous with excimer-laser-induced crystallization. A in-situ fluorine passivation by the proposed method was verified form XPS analysis and conductivity measurement. From experimental results, it has been shown that the proposed method is effective to improve the electrical characteristics, specially field-effect mobility, and the electrical stability of p-channel poly-Si TFTs. The improvement id due to fluorine passivation, which reduces the trap state density and forms the strong Si-F bonds in poly-Si channel and $SiO_2/poly-Si$ interface. From these results, the high performance poly-Si TFTs canbe obtained by employing the excimer-laser-induced fluorine passivation method.

• Korean Journal of Materials Research
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• v.10 no.3
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• pp.212-217
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• 2000

Dielectric thin films for TFT(thin film transistor)s, such as silicon nitride$(Si_3N_4)$ and silicon oxide$(SiO_2)$, are usually deposited at $200~300^{\circ}C$. In this study, authors have tried to form dielectric films not by deposition but by oxidation with ECR(Electron Cyclotron Resonance) oxygen plasma, to improve the interface properties was not intensionally heated during oxidation. THe oxidation was performed consecutively without breaking vacuum after the deposition of a-Si: H films on the substrate to prevent the introduction of impurities. In this study, especially pulse mode of microwave power has been firstly tried during FCR oxygen plasma formation. Compared with the case of the continuous wave mode, the oxidation with the pulsed ECR results in higher quality silicon oxide$SiO_X$ films in terms of stoichiometry of bonding, dielectric constants and surface roughness. Especially the surface roughness of the pulsed ECR oxide films dramatically decreased to one-third of that of the continuous wave mode cases.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.51-51
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.12
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• pp.1018-1022
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340 V breakdown voltage. The channel thickness was 3 urn and the channel doping concentration is $1e17\;cm^{-3}$. And we carried out thermal characteristics, too.

• Bulletin of the Korean Chemical Society
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• v.35 no.11
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• pp.3299-3302
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• 2014

The In2S3 thin films of tetragonal structure and In2O3 films of cubic structure were synthesized by a spin coating method from the organometallic compound precursor triethylammonium indium thioacetate ($[(Et)_3NH]^+[In(SCOCH_3)_4]^-$; TEA-InTAA). In order to determine the electron mobility of the spin-coated TEA-InTAA films, thin film transistors (TFTs) with an inverted structure using a gate dielectric of thermal oxide ($SiO_2$) was fabricated. These devices exhibited n-channel TFT characteristics with a field-effect electron mobility of $10.1cm^2V^{-1}s^{-1}$ at a curing temperature of $500^{\circ}C$, indicating that the semiconducting thin film material is applicable for use in low-cost, solution-processed printable electronics.

• Electrical & Electronic Materials
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• v.9 no.10
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• pp.1008-1012
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• 1996

I-V, C-V characteristics of inverted staggered type hydrogenerated amorphous silicon thin film transistor(a-Si:H TFT) was studied and experimentally verified. The results show that the log-log plot of drain current increased by voltage increase. The saturated drain current of DC output characteristics increased at a fixed gate voltage. According to the increase of gate voltage, activation energy of electron and the increasing width of Id at high voltage were decreased. Id saturation current saturated at high Vd over 4.5V, Vg-ld hysteresis characteristic curves occurred between -15V and 15V of Vg. Hysteresis current decreased at low voltage of -15V and increased at high voltage of 15V.