• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.103-103
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• 1999

CeO2 는 cubic 구조의 일종인 CeF2 구조를 가지며 격자 상수가 0.541nm로 Si의 격자 상수 0.543nm와 거의 비슷하여 Si과의 부정합도가 0.35%에 불과하여 CeO2를 Si 기판 위에 에피택셜하게 성장시킬 수 있는 가능성이 크다. 따라서 SOI(Silicon-On-Insulator) 구조의 실현을 위하여 Si 기판위에 CeO2를 에피택셜하게 성장시키려는 많은 노력이 있었다. 또한 CeO2 는 열 적으로 대단히 안정된 물질로서 금속/강유전체/반도체 전계효과 트랜지스터(MFSFET : metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이에 완충층으로 사용되어 강유전체의 구성 원자와 Si 원자들간의 상호 확산을 방지함으로써 경계면의 특성을 향상시기키 위해 사용된다. e-beam evaporation와 laser ablation에 의한 Si 기판 위의 CeO2 격자 성장에 관한 많은 보고서가 있다. 이 방법들은 대규모 생산 공정에서 사용하기 어려운 반면 RF-magnetron sputtering은 대규모 반도체 공정에 널리 쓰인다. Sputtering에 의한 Si 기판위의 CeO2 막의 성장에 관한 보고서의 수는 매우 적다. 이 논문에서는 Ce target을 사용한 reactive rf-magnetron sputtering에 의해 Si(100) 과 Si(111) 기판위에 성장된 CeO2 의 구조 및 전기적 특성을 보고하고자 한다. 주요한 증착 변수인 증착 power와 증착온도, Seed Layer Time이 성장막의 결정성에 미치는 영향을 XRD(X-Ray Diffractometry) 분석과 TED(Transmission Electron Diffration) 분석에 의해 연구하였고 CeO2 /Si 구조의 C-V(capacitance-voltage)특성을 분석함으로써 증차된 CeO2 막과 실리콘 기판과의 계면 특성을 연구하였다. CeO2 와 Si 사이의 계면을 TEM 측정에 의해 분석하였고, Ce와 O의 화학적 조성비를 RBS에 의해 측정하였다. Si(100) 기판위에 증착된 CeO2 는 $600^{\circ}C$ 낮은 증착률에서 seed layer를 하지 않은 조건에서 CeO2 (200) 방향으로 우선 성장하였으며, Si(111) 기판 위의 CeO2 박막은 40$0^{\circ}C$ 높은 증착률에서 seed layer를 2분이상 한 조건에서 CeO2 (111) 방향으로 우선 성장하였다. TEM 분석에서 CeO2 와 Si 기판사이에서 계면에서 얇은 SiO2층이 형성되었으며, TED 분석은 Si(100) 과 Si(111) 위에 증착한 CeO2 박막이 각각 우선 방향성을 가진 다결정임을 보여주었다. C-V 곡선에서 나타난 Hysteresis는 CeO2 박막과 Si 사이의 결함때문이라고 사료된다.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.208-213
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• 1998

Silicidation of the Co/Ti/Si bilayer system in which Ti is used as epitaxy promoter for $CoSi_2$has recently received much attention. The Co/Ti bilayer on the spacer oxide of gate electrode must be thermally stable at high temperatures for a salicide transistor to be fabricated successfully. In the $SiO_2$substrate was rapid-thermal annealed. The Sheet resistances of the Co/Ti bilayer increased substantially after annealing at $600^{\circ}C$, which is due to the agglomeration of the Co layer to reduce the interface energy between the Co layer and the $SiO_2$substrate. In the bilayer system insulating Ti oxide stoichiometric Ti oxide and silicide were not found after annealing.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.32-35
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• 2013

In this paper, a manufacturing process was developed for fabricating high-quality AlGaN/GaN high electron mobility transistors (HEMTs) on silicon carbide (SiC) substrates. Various conditions and processing methods regarding the ohmic contact and pre-metal-deposition $BCl_3$ etching processes were evaluated in terms of the device performance. In order to obtain a good ohmic contact performance, we tested a Ti/Al/Ta/Au ohmic contact metallization scheme under different rapid thermal annealing (RTA) temperature and time. A $BCl_3$-based reactive-ion etching (RIE) method was performed before the ohmic metallization, since this approach was shown to produce a better ohmic contact compared to the as-fabricated HEMTs. A HEMT with a 0.5 ${\mu}m$ gate length was fabricated using this novel manufacturing process, which exhibits a maximum drain current density of 720 mA/mm and a peak transconductance of 235 mS/mm. The X-band output power density was 6.4 W/mm with a 53% power added efficiency (PAE).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.47-50
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• 2000

This paper investigated structural and electrical properties of $Y_2$ $O_3$ as a buffer layer of single transistor FRAM (ferroelectric RAM). $Y_2$ $O_3$ buffer layers were deposited at a low substrate temperature below 40$0^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post-annealing temperature, and suppression of interfacial $SiO_2$ layer generation. For a well-fabricated sample, we achieved that leakage current density ( $J_{leak}$) in the order of 10$^{-7}$ A/$\textrm{cm}^2$, breakdown electric field ( $E_{br}$ ) about 2 MV/cm for $Y_2$ $O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_2$ $O_3$/Si as low as 8.72x1010 c $m^{-2}$ e $V^{-1}$ . The low interface states were obtained from very low lattice mismatch less than 1.75%.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.169-172
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• 2000

A-Si:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly-Si films were achieved by various anneal techniques ; isothermal, RTA, and excimer laser anneal. The TFT on as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from $200^{\circ}C$ to $1000^{\circ}C$. The TFT on poly-Si showed an improved $I_{on}/I_{off}$ ratio of $10^6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly-Si TFTs.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.67-67
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• 2000

CeO2는 cubic 구조의 일종인 CaR2 구조를 가지고 있으며 격자상수가 Si의 격장상수와 매우 비슷하여 Si 기판위에 에피텍셜하게 성장할 수 있는 가능성이 매우 크다. 따라서 SOI(silicon-on-insulator)구조의 실현을 위하여 Si 기판위에 CeO2 박막을 에피텍셜하게 성장시키려는 많은 노력이 있어왔다. 또한 metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이의 완충층으로 사용된다. 이러한 CeO2의 응용을 위해서는 Si 기판 위에 성장된 CeO2 박막의 방위성 및 CeO2/Si 구조의 전기적 특성을 알아보는 것이 매우 중요하다. 본 연구에서는 Si(100) 기판위에 CeO2(200)방향으로 성장하는 박막과 EcO2(111) 방향으로 성장하는 박막을 rf magnetron sputtering 방법으로 증착하여 각각의 구조적, 전기적 특성을 분석하였다. RCA 방법으로 세정한 P-type Si(100)기판위에 Ce target과 O2를 사용하여 CeO2(200) 및 CeO2(111)박막을 증착하였다. 증착후 RTA(rapid thermal annealing)방법으로 95$0^{\circ}C$, O2 분위기에서 5분간 열처리를 하였다 이렇게 제작된 CeO2 박막의 구조적 특성을 XRD(x-ray diffraction)방법으로 분석하였고, Al/CeO2/Si의 MIS(metal-insulator-semiconductor)구조를 제작하여 C-V (capacitance-voltage), I-V (current-voltage) 특성을 분석하였으며 TEM(transmission electron microscopy)으로 증착된 CeO2막과 Si 기판과의 계면 특성을 연구하였다. C-V특성에 있어서 CeO2(111)/Si은 CeO2(111)의 두께가 증가함에 따라 hysteresis windows가 증가한 방면 CeO2(200)/Si은 hysteresis windows가 아주 작을뿐만 아니라 CeO2(200)의 두께가 증가하더라도 hysteresis windos가 증가하지 않았다. CeO2(111)/Si과 CeO2(200)/Si의 C-V 특성의 차이는 CeO2(111)과 CeO2(200)이 Si 기판에 의해 받은 stress의 차이와 이에 따른 defect형성의 차이에 의한 것으로 사료된다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.161-168
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• 2001

Organic thin film transitors(TFTs) are of interest for use in broad area electronic applications. For example, in active matrix liquid crystal displays(AMLCDs), organic TFTs would allow the use of inexpensive, light-weight, flexible, and mechanically rugged plastic substrates as an alternative to the glass substrates needed for commonly used hydrogenated amorphous silicon(a-Si:H). Recently pentacene TFTs with carrier field effect, mobility as large as 2 $cm^2V^{-1}s^{-1}$ have been reported for TFTs fabricated on silicon substrates, and it is higher than that of a-Si:H. But these TFTs are fabricated on silicon wafer and $SiO_2$ was used as a gate insulator. $SiO_2$ deposition process requires a high insulator which is polyimide and photo acryl. We investigated trasfer and output characteristics of the thin film transistors having active layer of pentacene. We calculated field effect mobility and on/off ratio from transfer characteristics of pentacene thin film transistor, and measured IR absorption spectrum of polymide used as the gate dielectric layer. It was found that using the photo acryl as a gate insulator, threshold voltage decreased from -12.5 V to -7 V, field effect mobility increased from 0.012 $cm^2V^{-1}s^{-1}$ to 0.039 $cm^2V^{-1}s^{-1}$ , and on/off current ratio increased from $10^5\;to\;10^6$. It seems that TFTs using photo acryl gate insulator is apt to form channel than TFTs using polyimide gate insulator.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.