• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.339-343
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• 2005

Pt-$SrBi_2Nb_2O_9(SBN)-Pt-Y_2O_3-Si$ gate field effect transistors (MFMISFETs) have been fabricated and the SBN thin films are rapid thermal annealed in oxygen plasma. The grain size of the SBN becomes 4 times much larger than that of furnace annealed SBN films even at the same annealing temperature of $700^{\circ}C$, remnant polarization value of Pt-SBN-Pt is improved by 2 times. Using the rapid grain growth of SBN for the MFM-ISFET, memory window and programming characteristics of on/off states are fairly well improved.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1443-1445
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• 1996

Hydrogen passivation enhances the electrical characteristics of poly-Si TFT(Thin Film Transistor). However, the weak Si-H bonds, generated during hydrogenation, degrade the stability of the device. So, we carried out the passivation treatment with $NH_3$ or $N_2$. We compared the effect of $NH_3$ or $N_2$ passivation treatments with that of hydrogenation in terms of stability. Through the $NH_3$ passivation treatment, we obtained the most improved subthreshold swing of 1.2V/decade from the initial subthreshold swing of 1.56V/decade. When electrical stress was given, the $NH_3$ passivated devices showed best electrical stability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.576-581
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• 2005

In this paper. the a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. High k gate dielectric is required for on-current, threshold voltage and breakdown characteristics of TFT Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_3N_4$. Ferroelectric increases on-current and decreases threshold voltage of TFT and also ran improve breakdown characteristics.$SrTiO_4$ thin film is deposited by e-beam evaporation. Deposited films are annealed for 1 hour in N2 ambient at $150^{\circ}C\~600^{\circ}C$. Dielectric constant of ferroelectric is about 60-100 and breakdown field is about IMV/cm. In this paper, the TFT using ferroelectric consisted of double layer gate insulator to minimize the leakage current. a-SiN:H, a-Si:H (n-type a-Si:H) are deposited onto $SrTiO_3$ film to make MFNS(Metal/ferroelectric/a-SiN:H/a-Si:H) by PECVD. In this paper, TFR using ferroelectric has channel length of$8~20{\mu}m$ and channel width of $80~200{\mu}m$. And it shows that drain current is $3.4{\mu}A$at 20 gate voltage, $I_{on}/I_{off}$ is a ratio of $10^5\~10^8,\;and\;V_{th}$ is$4\~5\;volts$, respectively. In the case of TFT without having ferroelectric, it indicates that the drain current is $1.5{\mu}A$ at 20gate voltage and $V_{th}$ is $5\~6$ volts. If properties of the ferroelectric thin film are improved, the performance of TFT using this ferroelectric thin film can be advanced.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.87-87
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• 1999

본 연구에서는 Pulsed Laser Deposition(이하 PDL)방법을 이용하여 Si기판에 (Ba,Sr)TiO3(이하 BST)박막을 MFS-FET(Metal-Ferroelectric-Semiconductor Field-effect Transistor)구조로 제조하였으며 BST박막의 강유전성이 BST 박막에 유도되는 응력에 어떤 영향을 받는지 살펴보았다. 본 연구에서는 완충막을 사용함으로써 BST박막과 완충막간의 격자부정합을 이용하여 BST박막에 강유전성을 유도하려고 하였다. 또한 MFS-FET구조의 BST박막에 유도되는 응력조절을 위하여 BST박막과 완충막의 두께를 변화하였으며 XRD를 통한 구조 분석 및 C-V test를 통한 전기적 특성을 관찰을 하였다. PLD법을 통해서 epitaxial 성장된 BST 박막에서는 Si에 epitaxial 성장된 완충막과의 격자부정합에 의한 BST박막내의 자발분극의 발생이 예상된다. 따라서, 본 연구는 강유전체의 자발분극에 의하여 발생되는 C-V 이력현상이 BST박막과 완충막과의 격자부정합에 의한 응력에 의해 발생될 것으로 예상하여, BST 박막에 유도되는 응력과 C-V 이력현상의 관계를 통하여 상온에서 상유전성을 갖는 BST가 응력에 의하여 어느 정도의 강유전성을 나타내는지를 밝히기 위해 진행되었다. 본 연구에서 사용된 완충막은 YSZ(Yttria Stabilized Zirconia)박막으로 0.4mTorrO2 분위기 하에서 600~80$0^{\circ}C$의 온도에서 증착하여 상형성을 살펴보았고 $700^{\circ}C$에서 epitaxial 성장을 확인하였으며 두께는 30~$\AA$으로 변화하였다. 또한 BST박막은 완충막과의 전압분배를 고려해 300~2000$\AA$으로 두께를 변화를 시키며 증착하였다. MFS 구조에서 Al 전극을 사용하여 완충막과 BST박막간의 두께 변화에 따른 Capacitance - Voltage(C-V) 측정을 하였으며 이를 통하여 강유전상의 특성인 C-V 이력현상을 관찰하였다. 그 결과 YSZ 박막에서는 C-V 이력현상이 나타나지 않았으며 BST 박막에서는 약 1.2V의 C-V이력현상이 보였다.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.921-923
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• 1999

비휘발성 메모리의 고집적화와 적응학습형 뉴럴 소자의 실현을 위하여 1-트랜지스터 구조 강유전체 비휘발성 메모리(MFS-FET)를 SOI 기판위에 제작하고 평가하였다. 먼저 SBT($Sr_{0.8}Bi_{2.2}Ta_{2}O_{9}$)를 직접 Si위에 증착하고 C-V를 측정하여 1V의 메모리 윈도우를 얻음으로써 비휘발성 메모리로써의 동작가능성을 확인하였다. 또한 다양하게 게이트의 W/L 비를 바꾸어서 MFS-FET를 제작하여 다양한 드레인 전압-드레인 전류 특성을 얻었고 실제로 쓰기와 읽기 동작을 수행하여 MFS-FET가 비휘발성 메모리로써 제대로 동작하고 있음을 확인하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.60.2-60.2
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• 2011

본 연구에서는 Indium-free 및 gallium-free 기반의 산화물 TFT를 제작하기 위해 n-type $TiO_2$ 반도체 기반의 thin film transistor ($Mo/TiO_{2-x}/SiO_2/p+\;+Si$)를 oxygen deficient black $TiO_{2-x}$ 타겟을 이용하여 DC magnetron sputtering 공법으로 제작하고 그 특성을 분석하였다. DC magnetron sputtering 공법으로 성막된 $TiO_{2-x}$ semiconductor의 전기적, 광학적, 화학적 결합 에너지 및 구조적 특성 분석을 위해 semiconductor parameter analyzer (Aglient 4156-C), UV/Vis spectrometer, X-ray Photoelectron Spectroscopy, Transmission Electron Microscopy를 각각 이용하여 분석하였으며 이를 RTA 전/후 특성 비교를 통하여 관찰하였다. $TiO_{2-x}$ TFT의 소자 특성은 RTA 열처리 전/후 전형적인 insulator 특성에서 semiconductor 특성으로 변화되는 것을 관찰할 수 있었으며, 최적화된 열처리 공정에서 filed effect mobility 0.69 $cm^2$/Vs, on to off current ratio $2.04{\times}10^7$, sub-threshold swing 2.45 V/decade와 Vth 10.45 V를 확보할 수 있었다. 또한 RTA 열처리 후 밴드갭이 3.25에서 3.41로 확장되는 특성을 나타내었다. 특히 RTA 열처리 후 stoichiometric $TiO_2$ 상태와는 다른 $Ti^{2+}$, $Ti^{3+}$, $Ti^{4+}$ 등의 다양한 oxidation states가 관찰되었으며 이러한 oxidation states를 $TiO_{2-x}$ 박막에서의 oxygen deficient 상태와 연관시킴으로써 oxygen vacancy의 n-type dopant로의 거동을 확인하였다. $TiO_2$ 채널 기반의 TFT 특성을 통하여서 indium free 또는 gallium free 산화물 채널로써의 가능성을 확인하였다.

• ETRI Journal
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• v.24 no.4
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• pp.290-298
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• 2002

We present, for the first time, a prototype active-matrix field emission display (AMFED) in which an amorphous silicon thin-film transistor (a-Si TFT) and a molybdenum-tip field emitter array (Mo-tip FEA) were monolithically integrated on a glass substrate for a novel active-matrix cathode (AMC) plate. The fabricated AMFED showed good display images with a low-voltage scan and data signals irrespective of a high voltage for field emissions. We introduced a light shield layer of metal into our AMC to reduce the photo leakage and back channel currents of the a-Si TFT. We designed the light shield to act as a focusing grid to focus emitted electron beams from the AMC onto the corresponding anode pixel. The thin film depositions in the a-Si TFTs were performed at a high temperature of above 360°C to guarantee the vacuum packaging of the AMC and anode plates. We also developed a novel wet etching process for $n^+-doped$ a-Si etching with high etch selectivity to intrinsic a-Si and used it in the fabrication of an inverted stagger TFT with a very thin active layer. The developed a-Si TFTs performed well enough to be used as control devices for AMCs. The gate bias of the a-Si TFTs well controlled the field emission currents of the AMC plates. The AMFED with these AMC plates showed low-voltage matrix addressing, good stability and reliability of field emission, and good light emissions from the anode plate with phosphors.

• ETRI Journal
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• v.31 no.6
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• pp.660-666
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• 2009

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Zn-oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below $200^{\circ}C$, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as $Si_3N_4$ and $Al_2O_3$, the electrical properties are analyzed. After post-annealing at $200^{\circ}C$ for 1 hour in an $O_2$ ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a $Si_3N_4$ IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogen-based bonds. From constant-current stress tests of $I_d$ = 3 ${\mu}A$, an IGZO-TFT with heat-treated $Si_3N_4$ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.55-57
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• 2017

Amorphous oxide thin film transistors (TFTs) were fabricated with 0.5 wt% silicon doped zinc tin oxide (a-0.5SZTO) thin film deposited by radio frequency (RF) magnetron sputtering. In order to investigate the effect of annealing treatment on the electrical properties of TFTs, a-0.5SZTO thin films were annealed at three different temperatures ($300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 2 hours in a air atmosphere. The structural and electrical properties of a-0.5SZTO TFTs were measured using X-ray diffraction and a semiconductor analyzer. As annealing temperature increased from $300^{\circ}C$ to $500^{\circ}C$, no peak was observed. This provided crystalline properties indicating that the amorphous phase was observed up to $500^{\circ}C$. The electrical properties of a-0.5SZTO TFTs, such as the field effect mobility (${\mu}_{FE}$) of $24.31cm^2/Vs$, on current ($I_{ON}$) of $2.38{\times}10^{-4}A$, and subthreshold swing (S.S) of 0.59 V/decade improved with the thermal annealing treatment. This improvement was mainly due to the increased carrier concentration and decreased structural defects by rearranged atoms. However, when a-0.5SZTO TFTs were annealed at $700^{\circ}C$, a crystalline peak was observed. As a result, electrical properties degraded. ${\mu}_{FE}$ was $0.06cm^2/Vs$, $I_{ON}$ was $5.27{\times}10^{-7}A$, and S.S was 2.09 V/decade. This degradation of electrical properties was mainly due to increased interfacial and bulk trap densities of forming grain boundaries caused by the annealing treatment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.3
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• pp.147-151
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• 2016

Graphene has a monolayer crystal structure formed with C-atoms and has been used as a base layer of HETs (hot electron transistors). Graphene HETs have exhibited the operation at THz frequencies and higher current on/off ratio than that of Graphene FETs. In this article, we report on the preliminary results of current characteristics from the HETs which are fabricated utilizing highly doped Si collector, graphene base, and 5 nm thin $Al_2O_3$ tunnel layers between the base and Ti emitter. We have observed E-B forward currents are inherited to tunneling through $Al_2O_3$ layers, but have not noticed the Schottky barrier blocking effect on B-C forward current at the base/collector interface. At the common-emitter configuration, under a constant $V_{BE}$ between 0~1.2V, $I_C$ has increased linearly with $V_{CE}$ for $V_{CE}$ < $V_{BE}$ indicating the saturation region. As the $V_{CE}$ increases further, a plateau of $I_C$ vs. $V_{CE}$ has appeared slightly at $V_{CE}{\simeq}V_{BE}$, denoting forward-active region. With further increase of $V_{CE}$, $I_C$ has kept increasing probably due to tunneling through thin Schottky barrier between B/C. Thus the current on/off ration has exhibited to be 50. To improve hot electron effects, we propose the usage of low doped Si substrate, insertion of barrier layer between B/C, or substrates with low electron affinity.