• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.380-386
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• 1991

Hydrogen plasma-assisted epitaxial(PAE) growth of GaAs/Si and GaAs/Ge/Si with Ge buffer layer has been investigated. By means of photoluminescence, Nomarski microscopu, and $\alpha$-step, it could be known that GaAs on Si with Ge buffer layer has better crystalline quality than GaAs on Si without Ge buffer layer. The stoichiometry of GaAs layer on Si was confirmed by the depth profile of Auger electron spectroscope (AES). Also the native oxide(SiO$_2$) layer on Si substrate was plama-etched and the removal of the oxide layer was confirmed by AES. Photoluminescence peak wavelength of GaAs/Ge/Si with Ge buffer of 1\ulcorner thickness and GaAs growth rate of 160$\AA$/min was 8700$\AA$and FWHM was 12$\AA$.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.71-76
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• 1995

The thermal oxidation of Ge$_{0.2}$Si$_{0.8}$ in wet ambient has been investigated by Rutherford Backscattering Spectrometry(RBS). A uniform Ge$_{0.2}$Si$_{0.8}$O$_{2}$ oxide is formed at temperatures below 650.deg. C for polycrystalline and below 700.deg. C for single crystalline substrates. At higher temperatures Ge becomes depleted from the oxide and finally SiO$_{2}$ oxide is formed with Ge piled-ub behind it. The transition between the different oxide types depends also on the crystallinity of Ge$_{0.2}$Si$_{0.8}$. When a uniform Ge$_{0.2}$Si$_{0}$8/O$_{2}$ oxide grows, its thickness is proportional to the square root of the oxidation time, which suggests that the rate noting process is the diffusive transport of oxidant across the oxide. It is believed the oxidation is controlled by the competition between the diffusion of Ge or Si in Ge$_{0.2}$Si$_{0.8}$ and the movement of oxidation front.t.oxidation front.t.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.161-165
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• 1993

The geometrical and electronic structure of epitaxially grown Ge on Si(100) and Si(111) surfaces has been studied by scanning tunneling microscopy. Since Ge atoms could be distinguished from Si atoms by scanning tunneling spectroscopy and voltage dependent STM images, the growth mode of the added layer could be studied. On the (100) surface with a (2${\times}$1) reconstruction, Ge overlayer grow preferentially on the B type step edges at 720K. On the (111) surface, Ge overlayer also grow on the step edges with (7${\times}$7) and (5${\times}$5) structure depending on their coverage and annealing temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.21-22
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• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.165-165
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• 2011

기존 실리콘 박막 태양 전지는 적외선에 대한 감응도와 흡수도가 낮아서 광흡수율을 증가시킬 경우 효율의 효과적인 개선이 기대되어진다. 이를 개선하기 위해서 밴드갭이 Si에 비해 상대적으로 낮은 Ge을 도입함으로써 Si와 Ge 화합물을 형성할 경우 결정상태와 수소 함유량에 따라 밴드갭 조절이 가능하다. 또한 Ge는 Si에 비해 빛에 대한 감응도가 우수하여 광흡수율을 증가시킬수 있다. 단 SiGe 박막의 Ge 량이 일정량이상 많아질 경우 박막 내 결함 등의 생성으로 광변환 효율이 오히려 감소하므로 Ge 량의 적정화가 필요하다. 본 실험에 사용된 SiGe:H Layer는 SiH4 가스와 GeH4 가스를 혼합하여 증착하였고 증착장비는 PECVD를 이용하였다. GeH4/SiH4+GeH4 가스는 각각 0, 0.03, 0.1, 0.5, 1의 비율로 증착하였으며, 파워는 플라즈마의 방전특성을 알아본 후 최소파워를 이용하여 증착하였다. 이는 증착 시 플라즈마에 의한 박막 손상을 최소화하기 위함이다. Ellipsometry를 이용하여 박막의 두께와 optical bandgap을 측정하였고, FTIR, Raman scattering 등을 측정하였다.

• Journal of Korea Foundry Society
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• v.17 no.5
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• pp.458-464
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• 1997

Mg-Cu-Si과 Mg-Cu-Ge계 3원 합금에서 비정질 생성범위와 열적, 기계적 성질을 조사하였다. Mg-Cu-Si계에서는 $15{\sim}45%Cu$, $0{\sim}10%Si$, Mg-Cu-Ge계에서는 $15{\sim}45%Cu$, $0{\sim}5%Ge$의 조성범위에서 각각 비정질 단상이 생성되었고, $15{\sim}22.5%Cu$, 2.5%Si(or Ge)의 조성범위에서 생성되는 비정질상은 180도 밀착굽힘을 하여도 파단되지 않는 양호한 인성을 가지고 있었으며, $Mg_{82.5}Cu_{15}Ge_{2.5}$비정질합금의 최대인장강도는 800 MPa로 결정질 Mg기 합금의 최대치인 300 MPa에 비해 월등히 높은 값을 나타내었다. 그러고 비정질합금의 결정화는 다음과 같은 과정으로 일어났다. 1) Si(or Ge) ${\le}$ 2.5%: 비정질 ${\to}$ 비정질+$Mg_2Cu$+Mg ${\to}$ $Mg_2Cu$+Mg+$Mg_2Si$(or Ge), 2) Si(or Ge)=5%: 비정질 ${\to}$ $Mg_2Cu$+Mg+$Mg_2Si$(or Ge), 3) Si=10%: 비정질 ${\to}$ 비정질+$Mg_2Si$ ${\to}$ $Mg_2Si$+$Mg_2Cu$+Mg.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.916-923
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• 2004

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.

• Journal of electromagnetic engineering and science
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• v.3 no.1
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• pp.29-34
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• 2003

In this paper, we fabricated an 1.8 ㎓ differential VCO using a commercial 0.5 ${\mu}{\textrm}{m}$ SiGe BiCMOS process technology, The fabricated VCO consumes 16 ㎃ at 3 V supply voltage and has a 1.2 $\times$ 1.6 $mm^2$TEX>chip area. A phase noise measured at 100 KHz offset carrier is -110 ㏈c/Hz and a tuning range is 1795 MHz~1910 MHz when two varactor diodes are biased from 0 V to 3 V.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.422-422
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• 2004