• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.854-859
• /
• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.541-544
• /
• 1998

A SiGe p-channel MESFET using $\delta-doped$ layers is designed and the considerable enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double $\delta-doped$ layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes inthe spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of $0~300\AA$ and the Ge composition of 0~30% are investigated, and the saturation current is observed to be increased by 45% compared with a double $\delta-doped$ Si p-channel MESFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.5
• /
• pp.320-323
• /
• 2018

SiGe thin films were deposited by remote plasma enhanced chemical vapor deposition (RPE-CVD) at $400^{\circ}C$ using $SiH_4$ or $SiCl_4$ and $GeCl_4$ as the source of Si and Ge, respectively. The growth rate and the degree of crystallinity of the fabricated films were characterized by scanning electron microscopy and Raman analysis, respectively. The optical and electrical properties of SiGe films fabricated using $SiCl_4$ and $SiH_4$ source were comparatively studied. SiGe films deposited using $SiCl_4$ source showed a lower growth rate and higher crystallinity than those deposited using $SiH_4$ source. Ultraviolet and visible spectroscopy measurement showed that the optical band gap of SiGe is in the range of 0.88~1.22 eV.

• Journal of the Korean Vacuum Society
• /
• v.17 no.2
• /
• pp.156-159
• /
• 2008

The electrical characteristic of SiGe-on-SOI (SGOI) wafer with different Ge concentration were evaluated by pseudo-MOSFET. Epitaxial SiGe layers was grown directly on top of SOI with Ge concentrations of 16.2, 29.7, 34.3 and 56.5 at.%. As Ge concentration increased, leakage current increased and threshold voltage shifted from 3 V to 7 V in nMOSFET, from -7 V to -6 V in pMOSFET. The interface states between buried oxide and top of Si was significantly increased by the rapid thermal annealing (RTA) process, and so the electrical characteristic of SGOI wafer degraded. On the other hand, additional post RTA　annealing (PRA) showed that it was effective in decreasing the interface states generated by RTA processes and the electrical characteristic of SGOI wafer enhanced higher than initial state.

• 한국신재생에너지학회:학술대회논문집
• /
• 2010.06a
• /
• pp.83.1-83.1
• /
• 2010

Hydrogenated a-SiGe middle cell for triple junction solar cell was investigated with various process parameters. a-SiGe I-layer was deposited at substrate temperature $245^{\circ}C$ and hydrogen content(R) was up to 26.7. Low optical bandgap(1.45eV) of a-SiGe cell was applied for middle cell although a-SiGe single cell efficiency with low Ge content was higher. And this cell was applied to the middle cell of a glass superstrate type a-Si/a-SiGe/uc-Si triple junction solar cell. The triple junction solar cell was resulted in the initial efficiency of about 9%, area $0.25cm^2$, under global AM 1.5 illumination.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1995.11a
• /
• pp.42-42
• /
• 1995

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.113-114
• /
• 2007

Hole mobility characteristics of single surface channel and dual channel Si/SiGe structure are compared, where the former one consists of a relaxed SiGe buffer layer and a tensile strained Si layer on top, and for dual channel structure a compressively strained SiGe layer is inserted between them. Due to the difference of hole mobility enhancement factors of layers between them, hole mobility characteristics with respect to the Si cap thickness shows the opposite tend. Hole mobility increases with thicker Si cap for single channel structure, whereas it decreases with thicker Si cap for dual channel structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.12
• /
• pp.1080-1086
• /
• 2005

We have studied the Ge redistribution after dry oxidation and the oxide growth rate of $Si_{1-x}Ge_x$ epitaxial layer. Oxidation were performed at 700, 800, 900, and $1,000\;^{\circ}C$. After the oxidation, the results of RBS (Rutherford Back Scattering) & AES(Auger Electron Spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $Si_{1-x}Ge_x$ interface. It is shown that the presence of Ge at the $Si_{1-x}Ge_x$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700 and 800$^{\circ}C$, while it was decreased at both 900 and $1,000^{\circ}C$ as the Ge mole fraction was increased. The dry of idation rates were reduced for heavy Ge concentration, and large oxiidation time. In the parabolic growth region of $Si_{1-x}Ge_x$ oxidation, the parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the $1,000^{\circ}C$, AES showed that Ge peak distribution at the $Si_{1-x}Ge_x$ interface reduced by interdiffusion of silicon and germanium.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.95-95
• /
• 2008

본 연구에서는 SiGe p-MOSFET을 제작하여 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성을 측정하였다. Si 기판위에 성장한 $Si_{0.88}Ge_{0.12}$으로 제작된 SiGe p-MOSFET의 채널은 게이트 산화막과 20nm 정도의 Si Spacer 층으로 분리되어 있다. 게이트 산화막은 열산화에 의해 70$\AA$으로 성장되었고, 게이트 폭은 $25{\mu}m$, 게이트와 소스/드레인 사이의 거리는 2.5때로 제작되었다. 제작된 SiGe p-MOSFET은 빠른 동작 특성, 선형성, 저주파 노이즈 특성이 우수하였다. 제작된 SiGe p-MOSFET의 ESD 에 대한 소자의 신뢰성과 내성을 연구하기 위하여 SiGe P-MOSFET에 ESD를 lkV에서 8kV까지 lkV 간격으로 가한 후, SiGe P-MOSFET의 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성 변화를 분석 비교하였다.

• Journal of the Korean Vacuum Society
• /
• v.4 no.S1
• /
• pp.178-184
• /
• 1995

SiO2 위에 as-dep. 비정질 Si1-xGex 합금박막을 증착하기 위하여 Si2H6 와 GeH4 가스를 사용한 저압 화학 기상증착(LPCVD)에 관하여 연구하였다. 증착온도는 $400-500^{\circ}C$였으며, 공정압력은 0.5-1Torr 였다. 박막내의 Ge 함량은 온도 및 증착가스의 유량이 일정하면 공정압력이 증가함에 따라 증가하였고, 공정압력 및 증착가스의 유량이 일정하면 증착온도에 관계없이 일정하였다. 일정한 Si2H6가스의 표면반응은 박막내의 Ge 원자에 의해 촉진됨을 알 수 있었다. 조성이 일정한 Si1-xGex 박막의 증착속도는 증착온도 증가에 따라 Arrhenius 형태로 증가하여, Si, Si0.84Ge0.16,Si0.69Ge0.31박막증착의 활성화에너지는 각각 1.5, 1.13, 1 eV로서 박막내의 Ge함량이 증가함에 따라 활성화 에너지는 감소하였다.