• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.439-445
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• 2007

SiGe integrated circuits are being used in the field of high-speed wire/wireless communications and microwave systems due to the RF/high-speed analog characteristics and the easiness in the fabrication. Reducing the resistance variation in SiGe thin film resistors results in enhancing the reliability of integrated circuits. In this paper, we investigate the causes that generate the resistance nonuniformity after the silicon-based thin film resistor was fabricated, and consider the counter plan against that. Because the Ti-B precipitate, which formed during the silicide process of the SiGe thin film resistor, gives rise to the nonuniformity of SiGe resistors, the boron ions should be implanted as many as possible. In addition, the resistance deviation increases as the size of the contact hole that interconnects the SiGe resistor and the metal line decreases. Therefore, the size of the contact hole must be enlarged in order to reduce the resistance deviation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.4
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• pp.578-588
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• 1997

Poly-$Si_{1-x}Ge_x$ films on oxidized Si wafer were prepared by rapid thermal chemical vapor deposition using the $SiH_4$ and $GeH_4$ gaseous mixture at various deposition conditions. The deposition temperature, $SiH_4\;: GeH_4$ flow ratio and pressure were varied from 400 to $600^{\circ}C$, 1 : 0.1-2 : 1 and 1 to 50 torr, respectively. In this work, we have investigated the change of Ge composition of poly-$Si_{1-x}Ge_x$ films deposited with the variation of deposition parameters and the effect of Ge composition on the deposition rate. From the experimental results, it was observed that the deposition rate increased with increasing deposition temperature and Ge composition. On the other hand, the Ge composition decreased with increasing temperature. As the deposition pressure increased, the deposition rate and Ge composition were increased linearly to 10 torr but increased slowly above it, which has been attributed to the slower rate of surface reaction than mass transfer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.905-909
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• 2009

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

• ETRI Journal
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• v.25 no.4
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• pp.247-252
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• 2003

This paper presents results from experiments on laser-annealed SiGe-selective epitaxial growth (LA-SiGe-SEG). The SiGe-SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA-SiGe-SEG technique with highly doped Ge and an ultra shallow junction on p-type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA-SiGe-SEG technology is suitable for fabricating high-speed, low-power devices.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.1-7
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• 2004

In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.

• Journal of the Korean Vacuum Society
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• v.20 no.2
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• pp.77-85
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• 2011

The silicon-germanium (SiGe) alloy, which is compatible with silicon semiconductor technology and has a smaller band gap and a lower thermal conductivity than silicon, has been used to fabricate electronic devices such as transistors, photodetectors, solar cells, and thermoelectric devices. This paper reviews the application of SiGe alloys to electronic devices and related technical issues. Since the SiGe alloy comprises germanium whose band gap is smaller than silicon, its band gap is also smaller than that of silicon irrespective of the ratio of silicon to germanium. This narrow band gap of SiGe enables the base thickness of bipolar transistors to decrease without a loss in current gain so that it is possible to improve the speed of bipolar transistors by adopting the SiGe-base. In addition, the conversion efficiency of solar cells is enhanced by the absorption of long-wavelength light in the SiGe absorption layer. Phonon scattering caused by the irregular distribution of alloying elements induces the lower thermal conductivity of SiGe than those of pure silicon and germanium. Because a thin film layer with a low thermal conductivity suppresses thermal conduction through a thermal sink, the SiGe alloy is considered to be a promising material for silicon-based thermoelectric systems.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.4
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• pp.86-92
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• 1999

A SiGe p-channel MESFET using $\delta$-doped layers is designed and the considerabel enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double $\delta$-doped layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes in the spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of 0~300$\AA$ and the Ge composition of 0~30% are investigated, and saturation current is observed to be increased by 45% compared with a double $\delta$-doped Si p-channel MESFET.