• Proceedings of the KIEE Conference
• /
• 1998.11c
• /
• pp.735-736
• /
• 1998

Reduction of hot carrier degradation in MOS devices has been one of the most serious concerns for MOS-ULSIs. In this paper, three types of LDD structure for suppression of hot carrier degradation, such as spacer-induced degradation and decrease of performance due to increase of series resistance will be investigated. LDD-nMOSFETs used in this study had three different drain structure. (1) conventional ${\underline{S}}urface$ type ${\underline{L}}DD$(SL), (2) ${\underline{B}}uried$ type ${\underline{L}}DD$(BL), (3) ${\underline{S}}urface$urface ${\underline{I}}mplantation$ type LDD(SI). As a result, the surface implantation type LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.8
• /
• pp.733-737
• /
• 2008

In this paper, Ni-Co alloy was used to improve thermal stability of Ni Germanide. It was found that uniform germanide is obtained on epitaxial Ge-on-Si substrate by employing Ni-Co alloy. Moreover, neither agglomeration nor penetration is observed during post-germanidation annealing process. The thermal stability of Ni germanide using Ni-Co alloy is improved due to the less agglomeration of Germanide. Therefore, the proposed Ni-Co alloy is promising for highly thermal immune Ni germanide for nano scale Ge-MOSFETs technology.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.1
• /
• pp.88-96
• /
• 2016

In this paper, the GaN FET based phase-shift full-bridge dc-dc converter design is implemented. Switch characteristics of GaN FET were analyzed in detail by comparing state-of-the-art Si MOSFET. Owing to the low conduction resistance and parasitic capacitance, it is expected to GaN FET based power conversion system has improved performance. However, GaN FET is vulnerable to electric interference due to the relatively low threshold voltage and fast switching transient. Therefore, it is necessary to consider PCB layout to design GaN FET based power system because PCB layout is the main reason of stray inductance. To reduce the electric noise, gate voltage of GaN FET is analyzed according to operation mode of phase-shift full-bridge dc-dc converter. Two 600W phase-shifted full-bridge dc-dc converter are designed based on the result to evaluate effects of stray inductance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.1
• /
• pp.52-62
• /
• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.4
• /
• pp.297-304
• /
• 2017

The purpose of this paper is to analyze losses because of switching devices and the secondary side circuit diodes of 500 W full bridge dc-dc converter by applying gallium nitride (GaN) field-effect transistor (FET), which is one of the wide band gap devices. For the detailed device analysis, we translate the specific resistance relation caused by the GaN FET material property into algebraic expression, and investigate the influence of the GaN FET structure and characteristic on efficiency and system specifications. In addition, we mathematically compare the diode rectifier circuit loss, which is a full bridge dc-dc converter secondary side circuit, with the synchronous rectifier circuit loss using silicon metal-oxide semiconductor (Si MOSFET) or GaN FET, which produce the full bridge dc-dc converter analytical value validity to derive the final efficiency and loss. We also design the heat sink based on the mathematically derived loss value, and suggest the heat sink size by purpose and the heat divergence degree through simulation.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.96-98
• /
• 2018

본 논문에서는 800V 배터리 전기자동차 LDC용 낮은 스위치 전압정격을 갖는 새로운 소프트 스위칭 하프브리지 컨버터를 제안한다. 제안하는 컨버터는 입력이 직렬구조로써 입력전압의 절반으로 낮은 스위치의 전압정격을 갖기 때문에 600V의 Si-MOSFET를 사용할 수 있어 도통손실을 줄일 수 있으며 부분공진 동작으로 스위칭 손실 저감 효과를 갖고, 넓은 입력전압 및 부하영역에서 소프트 스위칭을 성취하여 높은 효율을 달성할 수 있으며 변압기의 직렬연결로 된 커패시터로 인해 자화 전류의 오프셋이 없다. 제안하는 소프트 스위칭 컨버터의 동작원리를 제시하고 시작품을 통해 본 논문의 타당성을 검증하였다.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.78-80
• /
• 2018

본 논문은 용량성 결합 플라즈마 응용 시스템을 위한 전류형 토폴로지 기반의 전력 변환장치 구조를 제안한다. 제안된 시스템은 독립적으로 제어된 두 개의 고 정밀 펄스 전류를 부하로 출력하는 병렬 연결된 전류형 전력 변환장치로 구성된다. 전체 회로 토폴로지는 네 가지 세부 부분; 바이어스 전류 발생기, 바이어스 전류 모듈레이터, 슬롭 전류 발생기, 슬롭 전류 모듈레이터로 구성되어 있다. 제안된 시스템은 빠른 과도 특성을 위해 1200V/90A급 SiC MOSFET 스위치를 사용하였다. 제안된 전력 변환장치는 4.5kV의 출력전압, 40A급 출력전류와 100ns급 전류 상승/하강 특성을 충족시키도록 설계되었다. 본 연구는 펄스 전류형 전력 변환회로를 제안함으로써 전압형 전력 변환장치에 비해 전압 스파이크 및 전압 파형 왜곡을 줄여 보다 정확한 출력 전압을 발생시킴으로써 용량성 결합 플라즈마 시스템의 안정도 및 정밀도를 향상시킬 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.735-738
• /
• 2000

This paper shows experimentally that oxide layer on the p-type Si-substrate can grow at low temperature(500$^{\circ}C$∼600$^{\circ}C$) using high pressure water vapor system. As the result of experiment, oxide layer growth rate is about 0.19${\AA}$/min at 500$^{\circ}C$, 0.43${\AA}$/min at 550$^{\circ}C$, 1.2${\AA}$/min at 600$^{\circ}C$ respectively. So, we know oxide layer growth follows reaction-controlled mechanism in given temperature range. Consequently, granting that oxide layer growth rate increases linearly to temperature over 600$^{\circ}C$, we can expect oxide growth rate is 5.2${\AA}$/min at 1000$^{\circ}C$. High pressure oxidation of silicon is particularly attractive for the thick oxidation of power MOSFET, because thermal oxide layers can grow at relatively low temperature in run times comparable to typical high-temperature, 1 atm conditions. For higher-temperature, high-pressure oxidation, the oxidation time is reduced significantly

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.18-19
• /
• 2017

This paper shows the design of the high voltage capacitor charger which using a modified series parallel resonant converter. The used silicon carbide Metal-Oxide Semiconductor Field Effect Transistor (SiC MOSFET) is proper for the few hundred kHz of high switching frequency to overcome the bulk resonant inductor and snubber capacitors. Furthermore, to increase the amount of the charging current, three phase delta transformer is used as well as the secondary sides are connected in parallel. In this paper, the design procedure of the high voltage capacitor charger is suggested and the output power is verified by the experimental results with the rated resistor load.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.1
• /
• pp.37-43
• /
• 2020

This study proposes a 7kW low-voltage DC-DC converter (LDC) using a coupled inductor (CI) for heavy hydrogen electric transport vehicles. The LDC uses a phase-shift manner for soft switching. SiC-MOSFET is used to reduce the loss of reverse recovery current through the use of a high switching frequency. LDC is require large transformer and inductor because of large output current. The size of transformer and inductor can be reduced by deviding the transformer and inductor into two pieces each. This work presents the experimental results of the proposed circuit.