• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.95-95
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• 2008

본 연구에서는 SiGe p-MOSFET을 제작하여 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성을 측정하였다. Si 기판위에 성장한 $Si_{0.88}Ge_{0.12}$으로 제작된 SiGe p-MOSFET의 채널은 게이트 산화막과 20nm 정도의 Si Spacer 층으로 분리되어 있다. 게이트 산화막은 열산화에 의해 70$\AA$으로 성장되었고, 게이트 폭은 $25{\mu}m$, 게이트와 소스/드레인 사이의 거리는 2.5때로 제작되었다. 제작된 SiGe p-MOSFET은 빠른 동작 특성, 선형성, 저주파 노이즈 특성이 우수하였다. 제작된 SiGe p-MOSFET의 ESD 에 대한 소자의 신뢰성과 내성을 연구하기 위하여 SiGe P-MOSFET에 ESD를 lkV에서 8kV까지 lkV 간격으로 가한 후, SiGe P-MOSFET의 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성 변화를 분석 비교하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.180-186
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• 2023

Positive bias temperature instability (PBTI) degradation of n⁺ and p⁺ poly-Si gate high-voltage(HV) SiO2 dielectric nMOSFETs was investigated. Unlike the expectation that degradation of n⁺/nMOSFET will be greater than p⁺/nMOSFET owing to the oxide electric field caused by the gate material difference, the magnitude of the PBTI degradation was greater for the p⁺/nMOSFET than for the n⁺/nMOSFET. To analyze the cause, the interface state and oxide charge were extracted for each case, respectively. Also, the carrier injection and trapping mechanism were analyzed using the carrier separation method. As a result, it has been verified that hole injection and trapping by the p⁺ poly-Si gate accelerates the degradation of p⁺/nMOSFET. The carrier injection and trapping processes of the n⁺ and p⁺ poly-Si gate high-voltage nMOSFETs in PBTI are detailed in this paper.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.226-227
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• 2016

본 논문은 SiC Mosfet Gate Driver에서 Overcurrent상황 발생시 Mosfet 양단의 전압을 검출함으로써 스위칭 소자를 보호하는 Desaturation detction circuit에 대해 다룬다. IGBT와 다르게 SiC Mosfet의 경우 ohmic 영역과 saturation영역의 구분이 명확하지 않기 때문에 과전류 발생시 Mosfet 양단 전압을 검출하는데 어려움이 있다. 따라서 이를 보완하기 위하여 Mosfet drain측에 새로운 회로를 추가로 설계함으로써 이를 보완하여 효과적으로 양단전압을 검출한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.682-684
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• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics over the temperature range of 300K and 77K. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.474-477
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• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics over the temperature range or 300K and 77K. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.353-360
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• 2017

Recently, due to physical limitation of Si based power semiconductor, development speed of switching power semiconductors is falling and it is difficult to expect any further performance improvements. SiC based power semiconductor with superior characteristic than Si-based power semiconductor have been developed to overcome these limitations. however, there is not method to apply for real system. Therefore, suggested the feasibility and solution for SiC-based power semiconductor system. design to 1kW class DC-DC boost converter and demonstrated the superiority of SiC MOSFET under the same operating conditions by analyzing switching frequency, duty ratio, voltage and current, and comparing with Si based power semiconductor through experimental efficiency according to each system load. The SiC MOSFET has high efficiency and fast switching speed, and can be designed with small inductors and capacitors which has the advantage of volume reduction of the entire system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.773-776
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• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.92-94
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• 2018

본 논문은 SiC MOSFET 디바이스를 사용하는 전력변환장치에서 Rogowski 코일을 이용하여 SiC MOSFET 디바이스에 흐르는 전류를 측정하여, 과전류를 검출하고 게이팅 신호를 차단하는 기법에 관하여 연구한다. SiC MOSFET는 소자의 특성으로 보편적으로 사용되는 과전류 검출 방법인 DeSAT 적용이 어렵기 때문에 Rogowski 코일을 사용하여 스위치 전류를 측정, 과전류를 검출한다. 본 논문에서는 PCB패턴 Rogowski 코일의 설계 방법뿐만 아니라 Rogowski 코일과 적분기의 대역폭에 대해서도 논의한다. 실험은 직류링크 커패시터에 SiC MOSFET 스위치 레그를 병렬로 연결하고, 직류링크 커패시터에 직류전압을 충전 후 스위치 레그를 약 6us정도 단락시켜 SiC MOSFET에 과전류를 발생시킨다. 이 때, 제안한 Rogowski 코일을 이용한 과전류 검출 및 차단 기법의 적용 전후를 비교하여 동작 및 성능(검출 및 차단 소요시간)을 확인한다. 마지막으로 실험 결과를 통해 본 논문에서 제안한 PCB패턴 Rogowski 코일을 이용하여 과전류 검출 및 차단 기법이 검증되었다.